[AMD Official Use Only - Internal Distribution Only] Acked-by: Evan Quan <[email protected]>
-----Original Message----- From: amd-gfx <[email protected]> On Behalf Of Alex Deucher Sent: Friday, June 5, 2020 11:40 PM To: [email protected]; Liang, Prike <[email protected]> Cc: Deucher, Alexander <[email protected]> Subject: [PATCH] drm/amdgpu/soc15: fix using ip discovery tables on renoir (v2) The PWR block moved into SMUIO, so the ip discovery table doesn't have an entry for PWR, but the register has the same absolute offset, so just patch up the offsets after updating the offsets from the IP discovery table. v2: PWR became SMUIO block 1. fix the mapping. Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 623745b2d8b3..dd17a8422111 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -686,6 +686,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) DRM_WARN("failed to init reg base from ip discovery table, " "fallback to legacy init method\n"); vega10_reg_base_init(adev); +} else { +/* PWR block was merged into SMUIO on renoir and became SMUIO block 1 */ +adev->reg_offset[PWR_HWIP][0] = adev->reg_offset[SMUIO_HWIP][1]; } } break; -- 2.25.4 _______________________________________________ amd-gfx mailing list [email protected] https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cevan.quan%40amd.com%7C3f359d67aa2d42c7f53d08d80966d087%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637269684501531639&sdata=K5%2BV%2Bo5cBNSAVgDk8NHQ%2F46YiRVB5rbbk6wy%2BSL9RM4%3D&reserved=0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
