[AMD Public Use]
Would it be better to put this code into amdgpu_gfx_off_ctrl()? Then we'll
handle this in all cases where we disable gfx off.
Alex
________________________________
From: Tianci Yin <tianci....@amd.com>
Sent: Tuesday, July 28, 2020 3:04 AM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Tuikov, Luben <luben.tui...@amd.com>; Deucher, Alexander
<alexander.deuc...@amd.com>; Zhang, Hawking <hawking.zh...@amd.com>; Xu, Feifei
<feifei...@amd.com>; Hesik, Christopher <christopher.he...@amd.com>; Swamy,
Manjunatha <manjunatha.sw...@amd.com>; Quan, Evan <evan.q...@amd.com>; Chen,
Guchun <guchun.c...@amd.com>; Feng, Kenneth <kenneth.f...@amd.com>; Yin, Tianci
(Rico) <tianci....@amd.com>
Subject: [PATCH] drm/amdgpu: reconfigure spm golden settings on Navi1x after
GFXOFF exit(v2)
From: "Tianci.Yin" <tianci....@amd.com>
On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit,
reconfigure the golden settings after GFXOFF exit.
Change-Id: I9358ba9c65f241c36f8a35916170b19535148ee9
Reviewed-by: Feifei Xu <Feifei x...@amd.com>
Signed-off-by: Tianci.Yin <tianci....@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 55463e7a11e2..41487123c207 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1309,6 +1309,7 @@ static int smu_enable_umd_pstate(void *handle,
struct smu_context *smu = (struct smu_context*)(handle);
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ struct amdgpu_device *adev = smu->adev;
if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
return -EINVAL;
@@ -1318,12 +1319,22 @@ static int smu_enable_umd_pstate(void *handle,
if (*level & profile_mode_mask) {
smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
smu_dpm_ctx->enable_umd_pstate = true;
- amdgpu_device_ip_set_powergating_state(smu->adev,
+ amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_PG_STATE_UNGATE);
- amdgpu_device_ip_set_clockgating_state(smu->adev,
+ amdgpu_device_ip_set_clockgating_state(adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_CG_STATE_UNGATE);
+
+ if (adev->asic_type >= CHIP_NAVI10 &&
+ adev->asic_type <= CHIP_NAVI12 &&
+ (adev->pm.pp_feature & PP_GFXOFF_MASK)) {
+ if (adev->gfx.funcs->init_spm_golden) {
+ dev_dbg(adev->dev,"GFXOFF exited,
re-init SPM golden settings\n");
+ amdgpu_gfx_init_spm_golden(adev);
+ } else
+ dev_warn(adev->dev,"Callback
init_spm_golden is NULL\n");
+ }
}
} else {
/* exit umd pstate, restore level, enable gfx cg*/
@@ -1331,10 +1342,10 @@ static int smu_enable_umd_pstate(void *handle,
if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
*level = smu_dpm_ctx->saved_dpm_level;
smu_dpm_ctx->enable_umd_pstate = false;
- amdgpu_device_ip_set_clockgating_state(smu->adev,
+ amdgpu_device_ip_set_clockgating_state(adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_CG_STATE_GATE);
- amdgpu_device_ip_set_powergating_state(smu->adev,
+ amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_PG_STATE_GATE);
}
--
2.17.1
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