On Mon, Sep 14, 2020 at 12:55 AM Shirish S <[email protected]> wrote: > > With IOMMU enabled, if SDPIF_MMIO_CNTRL_0 is not set > appropriately the system hangs without any trace > during S3. > > To ease debug and to ensure that the failure, if any, > was caused by a race conditions that disabled write access to > SDPIF_MMIO_CNTRL_0 register, warn the user about it. > > Signed-off-by: Shirish S <[email protected]>
Reviewed-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index d0645ad3446e..fc2d88dbe828 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -1546,8 +1546,11 @@ static void gmc_v9_0_init_golden_registers(struct > amdgpu_device *adev) > */ > void gmc_v9_0_restore_registers(struct amdgpu_device *adev) > { > - if (adev->asic_type == CHIP_RAVEN) > + if (adev->asic_type == CHIP_RAVEN) { > WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, > adev->gmc.sdpif_register); > + WARN_ON(adev->gmc.sdpif_register != > + RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); > + } > } > > /** > -- > 2.17.1 > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
