[AMD Public Use]

You shall by pass get_rev_id function call, instead of adding the check in the 
callback function.

For each hw generation, there could be several callback function implementation 
depending on whether the mmRCC_DEV0_EPF0_STRAP0 can be re-used.

It's error prone if we just take the change in specific callback. There is no 
guarantee people remember to add this check next time when working on the 
implementation.

Regards,
Hawking

-----Original Message-----
From: Khaire, Rohit <[email protected]> 
Sent: Tuesday, September 22, 2020 04:55
To: [email protected]
Cc: Tuikov, Luben <[email protected]>; Koenig, Christian 
<[email protected]>; Deucher, Alexander <[email protected]>; 
Xiao, Jack <[email protected]>; Zhang, Hawking <[email protected]>; Xu, 
Feifei <[email protected]>; Wang, Kevin(Yang) <[email protected]>; Yuan, 
Xiaojie <[email protected]>; Li, Rong (Zero) <[email protected]>; Min, Frank 
<[email protected]>; Khaire, Rohit <[email protected]>
Subject: [PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue for 
SRIOV

Signed-off-by: Rohit Khaire <[email protected]>
---
 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 7429f30398b9..4f611cd68940 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -51,8 +51,19 @@ static void nbio_v2_3_remap_hdp_registers(struct 
amdgpu_device *adev)
 
 static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)  {
-       u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+       u32 tmp;
+
+       if (amdgpu_sriov_vf(adev)) {
+               /* workaround on rev_id for sriov
+                * guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
+                * as a consequence, the rev_id and external_rev_id are wrong.
+                *
+                * workaround it by using PCI revision id.
+                */
+               return adev->pdev->revision;
+       }
 
+       tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
        tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
        tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
 
--
2.17.1
_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Reply via email to