[+Alex] I think this was added for Arcturus, which shares the same IH IP as Navi10 and needs to support virtualization.
Regards, Felix Am 2020-09-25 um 7:30 a.m. schrieb Zhang, Hawking: > [AMD Public Use] > > Hi Likun, > > Let's take a step back to check with Alex S why he add the ASIC type check > here. I'm under impression there was a change to use navi10_ih block for > arcturus, but haven't followed up closely yet. > > Regards, > Hawking > > -----Original Message----- > From: Gao, Likun <[email protected]> > Sent: Friday, September 25, 2020 16:56 > To: [email protected] > Cc: Zhang, Hawking <[email protected]>; Gao, Likun <[email protected]> > Subject: [PATCH] amdgpu/drm: cleanup navi10 ih logic about older ASIC > > From: Likun Gao <[email protected]> > > The ASIC which is older than navi10 will not call into navi10_ih related > function, so cleanup the related code path. > > Signed-off-by: Likun Gao <[email protected]> > Change-Id: Idf73b73f1f4f19031260c220798e5fffbb2cecd2 > --- > drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 105 +++---------------------- > 1 file changed, 9 insertions(+), 96 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c > b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c > index 74b1e7dc49a9..92b5dc2931b6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c > +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c > @@ -94,14 +94,7 @@ static void navi10_ih_enable_interrupts(struct > amdgpu_device *adev) > > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); > - if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { > - if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, > ih_rb_cntl)) { > - DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); > - return; > - } > - } else { > - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); > - } > + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); > > adev->irq.ih.enabled = true; > > @@ -109,15 +102,7 @@ static void navi10_ih_enable_interrupts(struct > amdgpu_device *adev) > ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, > RB_ENABLE, 1); > - if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { > - if (psp_reg_program(&adev->psp, > PSP_REG_IH_RB_CNTL_RING1, > - ih_rb_cntl)) { > - DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); > - return; > - } > - } else { > - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); > - } > + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); > adev->irq.ih1.enabled = true; > } > > @@ -125,15 +110,7 @@ static void navi10_ih_enable_interrupts(struct > amdgpu_device *adev) > ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, > RB_ENABLE, 1); > - if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { > - if (psp_reg_program(&adev->psp, > PSP_REG_IH_RB_CNTL_RING2, > - ih_rb_cntl)) { > - DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); > - return; > - } > - } else { > - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); > - } > + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); > adev->irq.ih2.enabled = true; > } > } > @@ -151,14 +128,7 @@ static void navi10_ih_disable_interrupts(struct > amdgpu_device *adev) > > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); > - if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { > - if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, > ih_rb_cntl)) { > - DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); > - return; > - } > - } else { > - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); > - } > + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); > > /* set rptr, wptr to 0 */ > WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); @@ -170,15 +140,7 @@ static > void navi10_ih_disable_interrupts(struct amdgpu_device *adev) > ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, > RB_ENABLE, 0); > - if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { > - if (psp_reg_program(&adev->psp, > PSP_REG_IH_RB_CNTL_RING1, > - ih_rb_cntl)) { > - DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); > - return; > - } > - } else { > - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); > - } > + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); > /* set rptr, wptr to 0 */ > WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); > WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); @@ -190,15 > +152,7 @@ static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) > ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, > RB_ENABLE, 0); > - if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { > - if (psp_reg_program(&adev->psp, > PSP_REG_IH_RB_CNTL_RING2, > - ih_rb_cntl)) { > - DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); > - return; > - } > - } else { > - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); > - } > + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); > /* set rptr, wptr to 0 */ > WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); > WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); @@ -298,14 > +252,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev) > ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, > !!adev->irq.msi_enabled); > - if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { > - if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, > ih_rb_cntl)) { > - DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); > - return -ETIMEDOUT; > - } > - } else { > - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); > - } > + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); > if (adev->irq.ih1.ring_size) > navi10_ih_reroute_ih(adev); > > @@ -357,15 +304,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev) > WPTR_OVERFLOW_ENABLE, 0); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, > RB_FULL_DRAIN_ENABLE, 1); > - if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { > - if (psp_reg_program(&adev->psp, > PSP_REG_IH_RB_CNTL_RING1, > - ih_rb_cntl)) { > - DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); > - return -ETIMEDOUT; > - } > - } else { > - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); > - } > + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); > /* set rptr, wptr to 0 */ > WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); > WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); @@ -383,15 > +322,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev) > ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); > ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); > > - if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { > - if (psp_reg_program(&adev->psp, > PSP_REG_IH_RB_CNTL_RING2, > - ih_rb_cntl)) { > - DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); > - return -ETIMEDOUT; > - } > - } else { > - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); > - } > + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); > /* set rptr, wptr to 0 */ > WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); > WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); @@ -672,24 > +603,6 @@ static int navi10_ih_sw_init(void *handle) > adev->irq.ih1.ring_size = 0; > adev->irq.ih2.ring_size = 0; > > - if (adev->asic_type < CHIP_NAVI10) { > - r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); > - if (r) > - return r; > - > - adev->irq.ih1.use_doorbell = true; > - adev->irq.ih1.doorbell_index = > - (adev->doorbell_index.ih + 1) << 1; > - > - r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); > - if (r) > - return r; > - > - adev->irq.ih2.use_doorbell = true; > - adev->irq.ih2.doorbell_index = > - (adev->doorbell_index.ih + 2) << 1; > - } > - > r = amdgpu_irq_init(adev); > > return r; > -- > 2.25.1 > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
