[AMD Public Use] BTW, this workaround is actually used to fix vbios issue that the partial writes was enabled on board without ECC capability and result to performance drop. I don't think this is related to parity check or something. So the comment inline is also not correct.
Regards, Hawking -----Original Message----- From: amd-gfx <[email protected]> On Behalf Of Zhang, Hawking Sent: Tuesday, September 29, 2020 16:31 To: Chen, Guchun <[email protected]>; [email protected]; Deucher, Alexander <[email protected]>; Li, Dennis <[email protected]>; Zhou1, Tao <[email protected]>; Clements, John <[email protected]> Subject: RE: [PATCH] drm/amdgpu: drop duplicated ecc check for vega10 (v3) [AMD Public Use] + if (adev->ras_features & (1 << AMDGPU_RAS_BLOCK__UMC)) { if (adev->df.funcs->enable_ecc_force_par_wr_rmw) adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); Hmm... this is still not correct. If the UMC ECC is enabled, we don't need to apply the workaround. Regards, Hawking -----Original Message----- From: Chen, Guchun <[email protected]> Sent: Tuesday, September 29, 2020 14:53 To: [email protected]; Deucher, Alexander <[email protected]>; Zhang, Hawking <[email protected]>; Li, Dennis <[email protected]>; Zhou1, Tao <[email protected]>; Clements, John <[email protected]> Cc: Chen, Guchun <[email protected]> Subject: [PATCH] drm/amdgpu: drop duplicated ecc check for vega10 (v3) The same ECC check has been executed in amdgpu_ras_init for vega10, prior to gmc_v9_0_late_init. v2: drop all atombios helper callings v3: use bit operation Signed-off-by: Guchun Chen <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 3dddbc60fe3d..9599946e4bee 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1193,21 +1193,13 @@ static int gmc_v9_0_late_init(void *handle) r = amdgpu_gmc_allocate_vm_inv_eng(adev); if (r) return r; - /* Check if ecc is available */ + + /* apply DF parity workaround */ if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) { - r = amdgpu_atomfirmware_mem_ecc_supported(adev); - if (!r) { - DRM_INFO("ECC is not present.\n"); + if (adev->ras_features & (1 << AMDGPU_RAS_BLOCK__UMC)) { if (adev->df.funcs->enable_ecc_force_par_wr_rmw) adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); - } else - DRM_INFO("ECC is active.\n"); - - r = amdgpu_atomfirmware_sram_ecc_supported(adev); - if (!r) - DRM_INFO("SRAM ECC is not present.\n"); - else - DRM_INFO("SRAM ECC is active.\n"); + } } if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count) -- 2.17.1 _______________________________________________ amd-gfx mailing list [email protected] https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Chawking.zhang%40amd.com%7C06c662b3015149395d5c08d86452077e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637369650776046907&sdata=zEH5g3uQtHPGeZNc2qIteRg%2B%2FlhehcKHf7G3I5He1WU%3D&reserved=0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
