Add VR shared rail info.
Change-Id: I6ea756c42586c10543489dbdf558ce88c2416e1c
Signed-off-by: Evan Quan <[email protected]>
Acked-by: Alex Deucher <[email protected]>
---
drivers/gpu/drm/amd/include/atombios.h | 4 +++-
drivers/gpu/drm/amd/pm/inc/smu74_discrete.h | 3 ++-
.../gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c | 14 ++++++++++++++
.../gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h | 1 +
.../drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c | 14 ++++++++++++++
5 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/atombios.h
b/drivers/gpu/drm/amd/include/atombios.h
index e6548bb6cad2..c1d7b1d0b952 100644
--- a/drivers/gpu/drm/amd/include/atombios.h
+++ b/drivers/gpu/drm/amd/include/atombios.h
@@ -5636,7 +5636,9 @@ typedef struct _ATOM_SMU_INFO_V2_1
{
ATOM_COMMON_TABLE_HEADER asHeader;
UCHAR ucSclkEntryNum; // for potential future extend, indicate
the number of ATOM_SCLK_FCW_RANGE_ENTRY_V1
- UCHAR ucReserved[3];
+ UCHAR ucSMUVer;
+ UCHAR ucSharePowerSource;
+ UCHAR ucReserved;
ATOM_SCLK_FCW_RANGE_ENTRY_V1 asSclkFcwRangeEntry[8];
}ATOM_SMU_INFO_V2_1;
diff --git a/drivers/gpu/drm/amd/pm/inc/smu74_discrete.h
b/drivers/gpu/drm/amd/pm/inc/smu74_discrete.h
index 899d6d8108c2..350889e408d2 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu74_discrete.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu74_discrete.h
@@ -271,7 +271,8 @@ struct SMU74_Discrete_DpmTable {
uint8_t VRHotLevel;
uint8_t LdoRefSel;
- uint8_t Reserved1[2];
+ uint8_t SharedRails;
+ uint8_t Reserved1;
uint16_t FanStartTemperature;
uint16_t FanStopTemperature;
uint16_t MaxVoltage;
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
index 0d8a693b77e0..a553ae312e65 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
@@ -1427,6 +1427,20 @@ int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr
*hwmgr, struct pp_atom_ctr
return 0;
}
+int atomctrl_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr, uint8_t
*shared_rail)
+{
+ ATOM_SMU_INFO_V2_1 *psmu_info =
+ (ATOM_SMU_INFO_V2_1 *)smu_atom_get_data_table(hwmgr->adev,
+ GetIndexIntoMasterTable(DATA, SMU_Info),
+ NULL, NULL, NULL);
+ if (!psmu_info)
+ return -1;
+
+ *shared_rail = psmu_info->ucSharePowerSource;
+
+ return 0;
+}
+
int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
struct pp_atom_ctrl__avfs_parameters *param)
{
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
index 3ef3ccfa6aa7..b3951b19fbfc 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
@@ -347,5 +347,6 @@ extern int atomctrl_get_edc_leakage_table(struct pp_hwmgr
*hwmgr,
AtomCtrl_EDCLeakgeTable *table,
uint16_t offset);
+extern int atomctrl_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr, uint8_t
*shared_rail);
#endif
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
index c4590a43a4f7..6afbd138f4ea 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
@@ -1016,6 +1016,16 @@ static int
polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
return 0;
}
+static void polaris10_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr
*)(hwmgr->smu_backend);
+ SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
+ uint8_t shared_rail;
+
+ if (!atomctrl_get_vddc_shared_railinfo(hwmgr, &shared_rail))
+ table->SharedRails = shared_rail;
+}
+
static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
{
struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -1041,6 +1051,10 @@ static int polaris10_populate_all_graphic_levels(struct
pp_hwmgr *hwmgr)
pp_atomctrl_clock_dividers_vi dividers;
uint32_t dpm0_sclkfrequency = levels[0].SclkSetting.SclkFrequency;
+ if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
+ ASICID_IS_P30(adev->pdev->device, adev->pdev->revision))
+ polaris10_get_vddc_shared_railinfo(hwmgr);
+
polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
for (i = 0; i < dpm_table->sclk_table.count; i++) {
--
2.28.0
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