On Thu, Dec 3, 2020 at 1:23 AM Sonny Jiang <[email protected]> wrote:
>
> Signed-off-by: Sonny Jiang <[email protected]>
Please provide a patch description. What is this and what does it do?
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 4f718ee803d0..3eaabcfca94a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -1080,6 +1080,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device
> *adev, int inst_idx, boo
>
> static int vcn_v3_0_start(struct amdgpu_device *adev)
> {
> + volatile struct amdgpu_fw_shared *fw_shared;
> struct amdgpu_ring *ring;
> uint32_t rb_bufsz, tmp;
> int i, j, k, r;
> @@ -1222,6 +1223,9 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
> tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
> WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
>
> + fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
> + fw_shared->multi_queue.decode_queue_mode |=
> FW_QUEUE_RING_RESET;
> +
> /* programm the RB_BASE for ring buffer */
> WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
> lower_32_bits(ring->gpu_addr));
> @@ -1234,19 +1238,25 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
> ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
> WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
> lower_32_bits(ring->wptr));
> + fw_shared->multi_queue.decode_queue_mode &=
> ~FW_QUEUE_RING_RESET;
> +
> + fw_shared->multi_queue.encode_generalpurpose_queue_mode |=
> FW_QUEUE_RING_RESET;
> ring = &adev->vcn.inst[i].ring_enc[0];
> WREG32_SOC15(VCN, i, mmUVD_RB_RPTR,
> lower_32_bits(ring->wptr));
> WREG32_SOC15(VCN, i, mmUVD_RB_WPTR,
> lower_32_bits(ring->wptr));
> WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
> WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI,
> upper_32_bits(ring->gpu_addr));
> WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
> + fw_shared->multi_queue.encode_generalpurpose_queue_mode &=
> ~FW_QUEUE_RING_RESET;
>
> + fw_shared->multi_queue.encode_lowlatency_queue_mode |=
> FW_QUEUE_RING_RESET;
> ring = &adev->vcn.inst[i].ring_enc[1];
> WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2,
> lower_32_bits(ring->wptr));
> WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2,
> lower_32_bits(ring->wptr));
> WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
> WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2,
> upper_32_bits(ring->gpu_addr));
> WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
> + fw_shared->multi_queue.encode_lowlatency_queue_mode &=
> ~FW_QUEUE_RING_RESET;
> }
>
> return 0;
> @@ -1595,6 +1605,7 @@ static int vcn_v3_0_stop(struct amdgpu_device *adev)
> static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state)
> {
> + volatile struct amdgpu_fw_shared *fw_shared;
> struct amdgpu_ring *ring;
> uint32_t reg_data = 0;
> int ret_code;
> @@ -1626,6 +1637,8 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device
> *adev,
>
> ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
>
> /* Restore */
> + fw_shared =
> adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
> +
> fw_shared->multi_queue.encode_generalpurpose_queue_mode |=
> FW_QUEUE_RING_RESET;
> ring = &adev->vcn.inst[inst_idx].ring_enc[0];
> ring->wptr = 0;
> WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO,
> ring->gpu_addr);
> @@ -1633,7 +1646,9 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device
> *adev,
> WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE,
> ring->ring_size / 4);
> WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR,
> lower_32_bits(ring->wptr));
> WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR,
> lower_32_bits(ring->wptr));
> +
> fw_shared->multi_queue.encode_generalpurpose_queue_mode &=
> ~FW_QUEUE_RING_RESET;
>
> +
> fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
> ring = &adev->vcn.inst[inst_idx].ring_enc[1];
> ring->wptr = 0;
> WREG32_SOC15(VCN, inst_idx,
> mmUVD_RB_BASE_LO2, ring->gpu_addr);
> @@ -1641,6 +1656,7 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device
> *adev,
> WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2,
> ring->ring_size / 4);
> WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2,
> lower_32_bits(ring->wptr));
> WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2,
> lower_32_bits(ring->wptr));
> +
> fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
>
> /* Unstall DPG */
> WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx,
> mmUVD_POWER_STATUS),
> --
> 2.25.1
>
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