On Wed, Feb 3, 2021 at 3:30 AM chen gong <[email protected]> wrote: > > For Vangogh, the offset values of some GC registers used in the > gfx_v10_0_setup_grbm_cam_remapping() function are not the same as those > of Sienna_Cichlid, so cannot be reused. > > Although gfx_v10_0_setup_grbm_cam_remapping() is not called now for > Vangogh, it is necessary to implement this patch in case we enable this > code in the future. > > Signed-off-by: chen gong <[email protected]>
Reviewed-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 56 > +++++++++++++++++++++++++++++++++- > 1 file changed, 55 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 8ac2af2..a9ce2a0 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -7029,9 +7029,63 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct > amdgpu_device *adev) > WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); > > switch (adev->asic_type) { > + case CHIP_VANGOGH: > + /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ > + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << > + GRBM_CAM_DATA__CAM_ADDR__SHIFT) | > + (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Vangogh) << > + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); > + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); > + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); > + > + /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ > + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << > + GRBM_CAM_DATA__CAM_ADDR__SHIFT) | > + (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Vangogh) > << > + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); > + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); > + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); > + > + /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ > + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) > << > + GRBM_CAM_DATA__CAM_ADDR__SHIFT) | > + (SOC15_REG_OFFSET(GC, 0, > mmVGT_TF_MEMORY_BASE_HI_Vangogh) << > + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); > + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); > + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); > + > + /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ > + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << > + GRBM_CAM_DATA__CAM_ADDR__SHIFT) | > + (SOC15_REG_OFFSET(GC, 0, > mmVGT_HS_OFFCHIP_PARAM_Vangogh) << > + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); > + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); > + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); > + > + /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ > + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << > + GRBM_CAM_DATA__CAM_ADDR__SHIFT) | > + (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Vangogh) > << > + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); > + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); > + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); > + > + /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ > + data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << > + GRBM_CAM_DATA__CAM_ADDR__SHIFT) | > + (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Vangogh) > << > + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); > + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); > + WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); > + > + /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ > + data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << > + GRBM_CAM_DATA__CAM_ADDR__SHIFT) | > + (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Vangogh) << > + GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); > + break; > case CHIP_SIENNA_CICHLID: > case CHIP_NAVY_FLOUNDER: > - case CHIP_VANGOGH: > case CHIP_DIMGREY_CAVEFISH: > /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ > data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
