v2: remove check for error during swsmu amdgpu_dpm_get_pp_num_states() call to
match previous powerplay behaviour
v3: removed smu implementation of powerplay get_power_limit, which clashed with
commit dfb3bb7fccb37
Resolved context clashes caused by commits 9485ed36411b7, 766e03739bce7
Modified Files
smu_set_power_limit() - modifed arg0 to match Powerplay API
set_power_limit
smu_sys_get_pp_table() - modifed signature to match Powerplay API
get_pp_table
smu_get_power_num_states() - modifed arg0 to match Powerplay API
get_pp_num_states
smu_get_current_power_state() - modifed arg0 to match Powerplay API
get_current_power_state
smu_sys_get_pp_feature_mask() - modifed signature to match Powerplay API
get_ppfeature_status
smu_sys_set_pp_feature_mask() - modifed arg0 to match Powerplay API
set_ppfeature_status
Other Changes
added 6 above smu Powerplay functions to swsmu_dpm_funcs
removed special smu handling of above functions and called through Powerplay
API
Signed-off-by: Darren Powell <darren.pow...@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 62 ++++++++---------------
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 12 ++---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 51 +++++++++++--------
3 files changed, 58 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 81ebeff599e2..34e5c4c4f280 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -125,6 +125,7 @@ static ssize_t amdgpu_get_power_dpm_state(struct device
*dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(ddev);
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
enum amd_pm_state_type pm;
int ret;
@@ -137,12 +138,7 @@ static ssize_t amdgpu_get_power_dpm_state(struct device
*dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- if (adev->smu.ppt_funcs->get_current_power_state)
- pm = smu_get_current_power_state(&adev->smu);
- else
- pm = adev->pm.dpm.user_state;
- } else if (adev->powerplay.pp_funcs->get_current_power_state) {
+ if (pp_funcs->get_current_power_state) {
pm = amdgpu_dpm_get_current_power_state(adev);
} else {
pm = adev->pm.dpm.user_state;
@@ -308,6 +304,7 @@ static ssize_t
amdgpu_set_power_dpm_force_performance_level(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(ddev);
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
enum amd_dpm_forced_level level;
enum amd_dpm_forced_level current_level = 0xff;
int ret = 0;
@@ -343,9 +340,7 @@ static ssize_t
amdgpu_set_power_dpm_force_performance_level(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev))
- current_level = smu_get_performance_level(&adev->smu);
- else if (adev->powerplay.pp_funcs->get_performance_level)
+ if (pp_funcs->get_performance_level)
current_level = amdgpu_dpm_get_performance_level(adev);
if (current_level == level) {
@@ -382,7 +377,7 @@ static ssize_t
amdgpu_set_power_dpm_force_performance_level(struct device *dev,
pm_runtime_put_autosuspend(ddev->dev);
return -EINVAL;
}
- } else if (adev->powerplay.pp_funcs->force_performance_level) {
+ } else if (pp_funcs->force_performance_level) {
mutex_lock(&adev->pm.mutex);
if (adev->pm.dpm.thermal_active) {
mutex_unlock(&adev->pm.mutex);
@@ -413,6 +408,7 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(ddev);
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
struct pp_states_info data;
int i, buf_len, ret;
@@ -425,11 +421,7 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- ret = smu_get_power_num_states(&adev->smu, &data);
- if (ret)
- return ret;
- } else if (adev->powerplay.pp_funcs->get_pp_num_states) {
+ if (pp_funcs->get_pp_num_states) {
amdgpu_dpm_get_pp_num_states(adev, &data);
} else {
memset(&data, 0, sizeof(data));
@@ -455,8 +447,8 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(ddev);
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
struct pp_states_info data;
- struct smu_context *smu = &adev->smu;
enum amd_pm_state_type pm = 0;
int i = 0, ret = 0;
@@ -469,13 +461,8 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- pm = smu_get_current_power_state(smu);
- ret = smu_get_power_num_states(smu, &data);
- if (ret)
- return ret;
- } else if (adev->powerplay.pp_funcs->get_current_power_state
- && adev->powerplay.pp_funcs->get_pp_num_states) {
+ if (pp_funcs->get_current_power_state
+ && pp_funcs->get_pp_num_states) {
pm = amdgpu_dpm_get_current_power_state(adev);
amdgpu_dpm_get_pp_num_states(adev, &data);
}
@@ -590,13 +577,7 @@ static ssize_t amdgpu_get_pp_table(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev)) {
- size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
- pm_runtime_mark_last_busy(ddev->dev);
- pm_runtime_put_autosuspend(ddev->dev);
- if (size < 0)
- return size;
- } else if (adev->powerplay.pp_funcs->get_pp_table) {
+ if (adev->powerplay.pp_funcs->get_pp_table) {
size = amdgpu_dpm_get_pp_table(adev, &table);
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
@@ -1010,9 +991,7 @@ static ssize_t amdgpu_get_pp_features(struct device *dev,
return ret;
}
- if (is_support_sw_smu(adev))
- size = smu_sys_get_pp_feature_mask(&adev->smu, buf);
- else if (adev->powerplay.pp_funcs->get_ppfeature_status)
+ if (adev->powerplay.pp_funcs->get_ppfeature_status)
size = amdgpu_dpm_get_ppfeature_status(adev, buf);
else
size = snprintf(buf, PAGE_SIZE, "\n");
@@ -3024,6 +3003,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct
device *dev,
char *buf)
{
struct amdgpu_device *adev = dev_get_drvdata(dev);
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int limit_type = to_sensor_dev_attr(attr)->index;
uint32_t limit = limit_type << 24;
ssize_t size;
@@ -3041,8 +3021,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct
device *dev,
if (is_support_sw_smu(adev)) {
smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
- } else if (adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->get_power_limit) {
-
adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit,
true);
+ } else if (pp_funcs && pp_funcs->get_power_limit) {
+ pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit,
true);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else {
size = snprintf(buf, PAGE_SIZE, "\n");
@@ -3059,6 +3039,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device
*dev,
char *buf)
{
struct amdgpu_device *adev = dev_get_drvdata(dev);
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int limit_type = to_sensor_dev_attr(attr)->index;
uint32_t limit = limit_type << 24;
ssize_t size;
@@ -3076,8 +3057,8 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device
*dev,
if (is_support_sw_smu(adev)) {
smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
- } else if (adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->get_power_limit) {
-
adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit,
false);
+ } else if (pp_funcs && pp_funcs->get_power_limit) {
+ pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit,
false);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else {
size = snprintf(buf, PAGE_SIZE, "\n");
@@ -3105,6 +3086,7 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device
*dev,
size_t count)
{
struct amdgpu_device *adev = dev_get_drvdata(dev);
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int limit_type = to_sensor_dev_attr(attr)->index;
int err;
u32 value;
@@ -3128,10 +3110,8 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device
*dev,
return err;
}
- if (is_support_sw_smu(adev))
- err = smu_set_power_limit(&adev->smu, value);
- else if (adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->set_power_limit)
- err =
adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
+ if (pp_funcs && pp_funcs->set_power_limit)
+ err = pp_funcs->set_power_limit(adev->powerplay.pp_handle,
value);
else
err = -EINVAL;
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 81ee621df448..6c0aa38fccba 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1239,7 +1239,7 @@ int smu_get_power_limit(struct smu_context *smu,
uint32_t *limit,
enum smu_ppt_limit_level limit_level);
-int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
+int smu_set_power_limit(void *handle, uint32_t limit);
int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type,
char *buf);
int smu_od_edit_dpm_table(struct smu_context *smu,
@@ -1296,10 +1296,10 @@ extern const struct amdgpu_ip_block_version
smu_v12_0_ip_block;
bool is_support_sw_smu(struct amdgpu_device *adev);
bool is_support_cclk_dpm(struct amdgpu_device *adev);
int smu_reset(struct smu_context *smu);
-int smu_sys_get_pp_table(struct smu_context *smu, void **table);
+int smu_sys_get_pp_table(void *handle, char **table);
int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
-int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info
*state_info);
-enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
+int smu_get_power_num_states(void *handle, struct pp_states_info *state_info);
+enum amd_pm_state_type smu_get_current_power_state(void *handle);
int smu_write_watermarks_table(struct smu_context *smu);
int smu_set_watermarks_for_clock_ranges(
struct smu_context *smu,
@@ -1325,8 +1325,8 @@ enum amd_dpm_forced_level smu_get_performance_level(void
*handle);
int smu_force_performance_level(struct smu_context *smu, enum
amd_dpm_forced_level level);
int smu_set_display_count(struct smu_context *smu, uint32_t count);
int smu_set_ac_dc(struct smu_context *smu);
-size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
-int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
+int smu_sys_get_pp_feature_mask(void *handle, char *buf);
+int smu_sys_set_pp_feature_mask(void *handle, uint64_t new_mask);
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t mask);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index b7fe56b9e33e..e2b885bd23a3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -48,9 +48,10 @@
static const struct amd_pm_funcs swsmu_pm_funcs;
-size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+int smu_sys_get_pp_feature_mask(void *handle, char *buf)
{
- size_t size = 0;
+ struct smu_context *smu = handle;
+ int size = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
@@ -64,8 +65,9 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu,
char *buf)
return size;
}
-int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
+int smu_sys_set_pp_feature_mask(void *handle, uint64_t new_mask)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -381,7 +383,7 @@ static void smu_restore_dpm_user_profile(struct smu_context
*smu)
smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
}
-int smu_get_power_num_states(struct smu_context *smu,
+int smu_get_power_num_states(void *handle,
struct pp_states_info *state_info)
{
if (!state_info)
@@ -417,8 +419,9 @@ bool is_support_cclk_dpm(struct amdgpu_device *adev)
}
-int smu_sys_get_pp_table(struct smu_context *smu, void **table)
+int smu_sys_get_pp_table(void *handle, char **table)
{
+ struct smu_context *smu = handle;
struct smu_table_context *smu_table = &smu->smu_table;
uint32_t powerplay_table_size;
@@ -2085,8 +2088,9 @@ int smu_get_power_limit(struct smu_context *smu,
return ret;
}
-int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
+int smu_set_power_limit(void *handle, uint32_t limit)
{
+ struct smu_context *smu = handle;
uint32_t limit_type = limit >> 24;
int ret = 0;
@@ -2663,8 +2667,9 @@ int smu_get_uclk_dpm_states(struct smu_context *smu,
return ret;
}
-enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
+enum amd_pm_state_type smu_get_current_power_state(void *handle)
{
+ struct smu_context *smu = handle;
enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2750,19 +2755,25 @@ int smu_gfx_state_change_set(struct smu_context *smu,
uint32_t state)
static const struct amd_pm_funcs swsmu_pm_funcs = {
/* export for sysfs */
- .set_fan_control_mode = smu_pp_set_fan_control_mode,
- .get_fan_control_mode = smu_get_fan_control_mode,
- .set_fan_speed_percent = smu_set_fan_speed_percent,
- .get_fan_speed_percent = smu_get_fan_speed_percent,
- .get_performance_level = smu_get_performance_level,
- .get_fan_speed_rpm = smu_get_fan_speed_rpm,
- .set_fan_speed_rpm = smu_set_fan_speed_rpm,
- .switch_power_profile = smu_switch_power_profile,
+ .set_fan_control_mode = smu_pp_set_fan_control_mode,
+ .get_fan_control_mode = smu_get_fan_control_mode,
+ .set_fan_speed_percent = smu_set_fan_speed_percent,
+ .get_fan_speed_percent = smu_get_fan_speed_percent,
+ .get_performance_level = smu_get_performance_level,
+ .get_current_power_state = smu_get_current_power_state,
+ .get_fan_speed_rpm = smu_get_fan_speed_rpm,
+ .set_fan_speed_rpm = smu_set_fan_speed_rpm,
+ .get_pp_num_states = smu_get_power_num_states,
+ .get_pp_table = smu_sys_get_pp_table,
+ .switch_power_profile = smu_switch_power_profile,
/* export to amdgpu */
- .set_mp1_state = smu_set_mp1_state,
+ .set_power_limit = smu_set_power_limit,
+ .set_mp1_state = smu_set_mp1_state,
/* export to DC */
- .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
- .asic_reset_mode_2 = smu_mode2_reset,
- .set_df_cstate = smu_set_df_cstate,
- .set_xgmi_pstate = smu_set_xgmi_pstate,
+ .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
+ .get_ppfeature_status = smu_sys_get_pp_feature_mask,
+ .set_ppfeature_status = smu_sys_set_pp_feature_mask,
+ .asic_reset_mode_2 = smu_mode2_reset,
+ .set_df_cstate = smu_set_df_cstate,
+ .set_xgmi_pstate = smu_set_xgmi_pstate,
};
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
