[AMD Official Use Only - Internal Distribution Only] Hi Darren, It would be better if the condition is " asic_type >=CHIP_NAVI10". We assume that from navi10, this restriction is on all. With this change, the patch is Reviewed-by: Kenneth Feng <[email protected]> Thanks.
-----Original Message----- From: Powell, Darren <[email protected]> Sent: Saturday, April 17, 2021 6:30 AM To: [email protected] Cc: Powell, Darren <[email protected]> Subject: [PATCH 3/3] amdgpu/pm: set pp_dpm_dcefclk to readonly on smu_v11 gpus Writing to dcefclk causes the gpu to become unresponsive, and requires a reboot. Patch prevents user from successfully writing to file pp_dpm_dcefclk on smu_vv11 parts and gives better user feedback that this operation is not allowed. Signed-off-by: Darren Powell <[email protected]> --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 204e34549013..317e9b47db53 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -1891,6 +1891,19 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ } } + if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { + /* SMU MP1 does not support dcefclk level setting */ + if (asic_type == CHIP_NAVI10 || + asic_type == CHIP_NAVI14 || + asic_type == CHIP_NAVI12 || + asic_type == CHIP_SIENNA_CICHLID || + asic_type == CHIP_NAVY_FLOUNDER || + asic_type == CHIP_DIMGREY_CAVEFISH ) { + dev_attr->attr.mode &= ~S_IWUGO; + dev_attr->store = NULL; + } + } + #undef DEVICE_ATTR_IS return 0; -- 2.25.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
