[AMD Official Use Only - Internal Distribution Only]

Acked-by: Alex Deucher <[email protected]>
________________________________
From: amd-gfx <[email protected]> on behalf of Aurabindo 
Pillai <[email protected]>
Sent: Wednesday, April 21, 2021 3:17 PM
To: [email protected] <[email protected]>
Cc: Lakha, Bhawanpreet <[email protected]>; Kazlauskas, Nicholas 
<[email protected]>; R, Bindu <[email protected]>
Subject: [PATCH] drm/amd/display: get socBB from VBIOS for dcn302

[why]
Some SOC BB paramters may vary per SKU, and it does
not make sense for driver to hardcode these values.
This change was added for dcn30 and dcn301, but not
for dcn302

[how]
Parse the values from VBIOS if available, and use
them if valid

Fixes: 93669c8e48 ("drm/amd/display: get socBB from VBIOS")
Signed-off-by: Aurabindo Pillai <[email protected]>
---
 .../amd/display/dc/dcn302/dcn302_resource.c   | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index fc2dea243d1b..f44814d15206 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -1101,6 +1101,26 @@ static bool init_soc_bounding_box(struct dc *dc,  struct 
resource_pool *pool)
         loaded_ip->max_num_dpp = pool->pipe_count;
         loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
         dcn20_patch_bounding_box(dc, loaded_bb);
+
+       if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
+               struct bp_soc_bb_info bb_info = { 0 };
+
+               if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
+                           dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
+                       if (bb_info.dram_clock_change_latency_100ns > 0)
+                               dcn3_02_soc.dram_clock_change_latency_us =
+                                       bb_info.dram_clock_change_latency_100ns 
* 10;
+
+                       if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
+                               dcn3_02_soc.sr_enter_plus_exit_time_us =
+                                       
bb_info.dram_sr_enter_exit_latency_100ns * 10;
+
+                       if (bb_info.dram_sr_exit_latency_100ns > 0)
+                               dcn3_02_soc.sr_exit_time_us =
+                                       bb_info.dram_sr_exit_latency_100ns * 10;
+               }
+       }
+
         return true;
 }

--
2.31.1

_______________________________________________
amd-gfx mailing list
[email protected]
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Calexander.deucher%40amd.com%7Cd4786559160d4972759e08d904fa2c5d%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637546294804838871%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=qVnczJLExg%2FX2JaAh4euZPDU%2F5HO1fKscQ0XYjVrk5I%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Reply via email to