[AMD Public Use]
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
________________________________
From: YuBiao Wang <yubiao.w...@amd.com>
Sent: Thursday, May 13, 2021 6:33 AM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Grodzovsky, Andrey <andrey.grodzov...@amd.com>; Quan, Evan
<evan.q...@amd.com>; Chen, Horace <horace.c...@amd.com>; Tuikov, Luben
<luben.tui...@amd.com>; Koenig, Christian <christian.koe...@amd.com>; Deucher,
Alexander <alexander.deuc...@amd.com>; Xiao, Jack <jack.x...@amd.com>; Zhang,
Hawking <hawking.zh...@amd.com>; Liu, Monk <monk....@amd.com>; Xu, Feifei
<feifei...@amd.com>; Wang, Kevin(Yang) <kevin1.w...@amd.com>; Xiaojie Yuan
<xiaojie.y...@amd.com>; Wang, YuBiao <yubiao.w...@amd.com>
Subject: [PATCH] drm/amd/amdgpu: psp program IH_RB_CTRL on sienna_cichlid
[Why]
IH_RB_CNTL is blocked by PSP so we need to ask psp to help config it.
[How]
Move psp ip block before ih, and use psp to program IH_RB_CNTL under sriov.
Signed-off-by: YuBiao Wang <yubiao.w...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++++++++++++++++++--
drivers/gpu/drm/amd/amdgpu/nv.c | 12 +++++++++---
2 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index f4e4040bbd25..5ee923ccdeb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -151,7 +151,15 @@ static int navi10_ih_toggle_ring_interrupts(struct
amdgpu_device *adev,
/* enable_intr field is only valid in ring0 */
if (ih == &adev->irq.ih)
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1
: 0));
- WREG32(ih_regs->ih_rb_cntl, tmp);
+
+ if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+ if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
+ DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+ return -ETIMEDOUT;
+ }
+ } else {
+ WREG32(ih_regs->ih_rb_cntl, tmp);
+ }
if (enable) {
ih->enabled = true;
@@ -261,7 +269,15 @@ static int navi10_ih_enable_ring(struct amdgpu_device
*adev,
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
}
- WREG32(ih_regs->ih_rb_cntl, tmp);
+
+ if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+ if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
+ DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+ return -ETIMEDOUT;
+ }
+ } else {
+ WREG32(ih_regs->ih_rb_cntl, tmp);
+ }
if (ih == &adev->irq.ih) {
/* set the ih ring 0 writeback address whether it's enabled or
not */
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 75d1f9b939b2..2ec5d4e1f363 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -764,9 +764,15 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_SIENNA_CICHLID:
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
- amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
- if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
- amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+ if (!amdgpu_sriov_vf(adev)) {
+ amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+ if (likely(adev->firmware.load_type ==
AMDGPU_FW_LOAD_PSP))
+ amdgpu_device_ip_block_add(adev,
&psp_v11_0_ip_block);
+ } else {
+ if (likely(adev->firmware.load_type ==
AMDGPU_FW_LOAD_PSP))
+ amdgpu_device_ip_block_add(adev,
&psp_v11_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+ }
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
is_support_sw_smu(adev))
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
--
2.25.1
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