WIth Kevin's comments addressed, the patch is: Reviewed-by: Alex Deucher <[email protected]>
On Tue, May 18, 2021 at 5:36 AM Wang, Kevin(Yang) <[email protected]> wrote: > > [AMD Official Use Only] > > > > > ________________________________ > From: amd-gfx <[email protected]> on behalf of Aaron Liu > <[email protected]> > Sent: Tuesday, May 18, 2021 2:26 PM > To: [email protected] <[email protected]> > Cc: Deucher, Alexander <[email protected]>; Huang, Ray > <[email protected]>; Liu, Aaron <[email protected]> > Subject: [PATCH] drm/amdgpu: modify system reference clock source for navi+ > > Starting from Navi+, the rlc reference clock is used for system clock > from vbios gfx_info table. It is incorrect to use core_refclk_10khz of > vbios smu_info table as system clock. > > Signed-off-by: Aaron Liu <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c > index 8c417014ca89..83ca58426139 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c > @@ -546,6 +546,21 @@ int amdgpu_atomfirmware_get_clock_info(struct > amdgpu_device *adev) > ret = 0; > } > > + /* if asic is Navi+, the rlc reference clock is used for system clock > + * from vbios gfx_info table */ > + if (adev->asic_type >= CHIP_NAVI10) { > + index = > get_index_into_master_table(atom_master_list_of_data_tables_v2_1, > + gfx_info); > + if (amdgpu_atom_parse_data_header(mode_info->atom_context, > index, NULL, > + &frev, &crev, &data_offset)) { > + struct atom_gfx_info_v2_2 *gfx_info = (struct > atom_gfx_info_v2_2*) > + (mode_info->atom_context->bios + data_offset); > + if ((frev >= 2) && (crev >= 2)) > [kevin]: > There is a hidden danger here. We can't assume that the higher version (frev) > is compatible with old one. > the code should change to if (frev == 2) && (crev >= 2)) {} ... > > + spll->reference_freq = > le32_to_cpu(gfx_info->rlc_gpu_timer_refclk); > + ret = 0; > + } > + } > + > return ret; > } > > -- > 2.25.1 > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7CKevin1.Wang%40amd.com%7C28bc3524cc2b430f8ee108d919c6494d%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637569161701557512%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=kD9yMGIWNpeCZc87I%2B4UufLoAssTGQc73DRjOx4ipXM%3D&reserved=0 > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
