On Wed, Jul 28, 2021 at 9:33 PM Zhang, Yifan <[email protected]> wrote: > > Hi Alex, > > No, it won't break gfxoff. The "gfxoff broken" issue we saw last time has > been fixed on CP firmware update for Renoir, and this patch changes doorbell > range setting specifically for Renoir, not covering the other ASICs. I think > it is better to change doorbell range setting per ASIC to mitigate possible > side effects. >
Thanks. Do we need a firmware version check to determine when to set the range differently? Alex > BRs, > Yifan > > -----Original Message----- > From: Alex Deucher <[email protected]> > Sent: Wednesday, July 28, 2021 9:46 PM > To: Zhang, Yifan <[email protected]> > Cc: amd-gfx list <[email protected]> > Subject: Re: [PATCH v2] drm/amdgpu: fix the doorbell missing when in CGPG > issue for renoir. > > On Wed, Jul 28, 2021 at 2:10 AM Yifan Zhang <[email protected]> wrote: > > > > If GC has entered CGPG, ringing doorbell > first page doesn't wakeup GC. > > Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround this issue. > > > > Signed-off-by: Yifan Zhang <[email protected]> > > I assume this won't break gfxoff? The last time we changed this, it broke a > bunch of scenarios. Won't this cause just about all doorbells to wake gfx? > > Alex > > > --- > > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++++++- > > 1 file changed, 9 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > index 03acc777adf7..70b64b510743 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > @@ -3675,7 +3675,15 @@ static int gfx_v9_0_kiq_init_register(struct > > amdgpu_ring *ring) > > if (ring->use_doorbell) { > > WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, > > (adev->doorbell_index.kiq * 2) << > > 2); > > - WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, > > + /* In renoir, if GC has entered CGPG, ringing doorbell > > > first page > > + * doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to > > + * workaround this issue. > > + */ > > + if (adev->asic_type == CHIP_RENOIR) > > + WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, > > + (adev->doorbell.size - 4)); > > + else > > + WREG32_SOC15(GC, 0, > > + mmCP_MEC_DOORBELL_RANGE_UPPER, > > (adev->doorbell_index.userqueue_end > > * 2) << 2); > > } > > > > -- > > 2.25.1 > > > > _______________________________________________ > > amd-gfx mailing list > > [email protected] > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist > > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cyi > > fan1.zhang%40amd.com%7C4a2605541c22483b4a3a08d951ce097c%7C3dd8961fe488 > > 4e608e11a82d994e183d%7C0%7C0%7C637630767650055129%7CUnknown%7CTWFpbGZs > > b3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D > > %7C1000&sdata=1TIsNslKHeSNNMDR3MHPaIiP%2BSLVrr5cEfAbCmvZlCw%3D& > > ;reserved=0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
