Hi Kenneth, I understand that changing voltage 'standalone' is not a good idea. In that case, would it be possible to change the voltage table so that it would give a lower clock on certain voltage?
For example, I would like to change sclk 900, vddc: 1050 to sclk 800, vddc: 1050 Thanks On Mon, Aug 23, 2021, 14:59 <[email protected]> wrote: > Send amd-gfx mailing list submissions to > [email protected] > > To subscribe or unsubscribe via the World Wide Web, visit > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > or, via email, send a message with subject or body 'help' to > [email protected] > > You can reach the person managing the list at > [email protected] > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of amd-gfx digest..." > > > Today's Topics: > > 1. RE: Voltage control on Southern Island GPU using radeon > driver (Feng, Kenneth) > 2. RE: [PATCH] drm/amdgpu: add missing cleanups for Polaris12 > UVD/VCE on suspend (Quan, Evan) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Mon, 23 Aug 2021 07:11:10 +0000 > From: "Feng, Kenneth" <[email protected]> > To: "Koenig, Christian" <[email protected]>, Evans Jahja > <[email protected]>, "[email protected]" > <[email protected]> > Subject: RE: Voltage control on Southern Island GPU using radeon > driver > Message-ID: > < > by5pr12mb55607f9193f1a315210d1b838e...@by5pr12mb5560.namprd12.prod.outlook.com > > > > Content-Type: text/plain; charset="utf-8" > > [AMD Official Use Only] > > Hi Evans > I'm sorry but I don't suggest you manually control the standalone voltage > because it's predefined with the clock value. > A decrease of voltage could hit the hardware critical path. You may need > to change the clock and voltage together, we call it dpm level change. > Thanks. > > > -----Original Message----- > From: amd-gfx <[email protected]> On Behalf Of > Christian K?nig > Sent: Monday, August 23, 2021 2:26 PM > To: Evans Jahja <[email protected]>; [email protected] > Subject: Re: Voltage control on Southern Island GPU using radeon driver > > [CAUTION: External Email] > > Hi Evans, > > in general the voltage tables are stored in the atombios and the best > advice I can give you is to first double check if there isn't an updated > BIOS for your hardware. > > But Alex is the expert on power management, especially for those older > hardware generations. Maybe he has another idea what to try. > > Regards, > Christian. > > Am 23.08.21 um 03:56 schrieb Evans Jahja: > > Hi, I have a HAINAN GPU below: > > > > lspci -nn > > 0a:00.0 Display controller [0380]: Advanced Micro Devices, Inc. > > [AMD/ATI] Sun LE [Radeon HD 8550M / R5 M230] [1002:666f] > > > > I run linux 5.13.12 on Arch on a Lenovo B40-70 laptop. > > > > I'm trying to understand more on how voltage control works and how I > > can modify the voltage for doing overvoltage / undervoltage on my GPU. > > The reason is I am observing how running programs under high GPU load > > (glmark2) would lead to crashes when I use dpm=1 in either radeon or > > amdgpu driver, which seems to happen when I am reaching power level 4 > > (sclk 900MHz), while a lighter program like glxgears could run and > > switch power levels between 0,1,2 without issue under both drivers. I > > believe my laptop might be faulty, but I would like to take this > > opportunity to try fixing it from the driver's side so that it can run > > anyway, however limited. > > > > Right now, I have managed to increase the performance of my GPU by > > manually overwriting the sclk to 630MHz in all performance_levels in > > radeon_pm.c, which surprises me as overriding the clock was not > > possible for me to do previously via sysfs. > > > > I've managed to tweak both sclk and mclk (or so I believe), but I > > still cannot tweak the voltage (vddc). The reason is, if I increase > > the sclk to 650MHz, the lockup will happen again. Changing the > > pl->vddc variable does not seem to do anything. After various tracing > > with printk, I understand that on my system: > > > > pi->voltage_control = radeon_atom_is_voltage_gpio(rdev, > > SET_VOLTAGE_TYPE_ASIC_VDDC, > > VOLTAGE_OBJ_GPIO_LUT) > > > > this returns false, while: > > > > si_pi->voltage_control_svi2 = > > radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, > > VOLTAGE_OBJ_SVID2); > > > > This returns true, so I believe my system is using SVI2 somehow to set > > the voltage. Having no experience with SVI2, I read online and found > > out that SVI2 is a voltage regulator that uses Data / Clock pins to > > clock-in 8 bits of information and convert it to some voltage value > > between OFF, 0.5V -> 1.5V, offering fine control based on some look up > > table. > > > > My questions are as follows: > > Is it possible for me to modify my system so that I can manually > > adjust the voltage to my GPU? > > > > Thank you very much in advance. This is the first time I deal with > > kernel drivers, so any guidance on the matter helps a lot. > > > > - Evans > > > > > > ------------------------------ > > Message: 2 > Date: Mon, 23 Aug 2021 07:59:36 +0000 > From: "Quan, Evan" <[email protected]> > To: Alex Deucher <[email protected]> > Cc: "Lazar, Lijo" <[email protected]>, "Zhu, James" > <[email protected]>, "[email protected]" > <[email protected]>, "Liu, Leo" <[email protected]>, > "Deucher, Alexander" <[email protected]>, "Chen, Guchun" > <[email protected]>, "Pan, Xinhui" <[email protected]> > Subject: RE: [PATCH] drm/amdgpu: add missing cleanups for Polaris12 > UVD/VCE on suspend > Message-ID: > < > dm6pr12mb261946019274a3f1b5c09995e4...@dm6pr12mb2619.namprd12.prod.outlook.com > > > > Content-Type: text/plain; charset="utf-8" > > [AMD Official Use Only] > > > > > -----Original Message----- > > From: Alex Deucher <[email protected]> > > Sent: Friday, August 20, 2021 10:23 PM > > To: Quan, Evan <[email protected]> > > Cc: Lazar, Lijo <[email protected]>; Zhu, James <[email protected]>; > > [email protected]; Liu, Leo <[email protected]>; Deucher, > > Alexander <[email protected]>; Chen, Guchun > > <[email protected]>; Pan, Xinhui <[email protected]> > > Subject: Re: [PATCH] drm/amdgpu: add missing cleanups for Polaris12 > > UVD/VCE on suspend > > > > On Thu, Aug 19, 2021 at 10:15 PM Quan, Evan <[email protected]> wrote: > > > > > > [AMD Official Use Only] > > > > > > > > > > > > > > > > > > > > > > > > From: Lazar, Lijo <[email protected]> > > > Sent: Thursday, August 19, 2021 10:36 PM > > > To: Zhu, James <[email protected]>; Quan, Evan > > <[email protected]>; > > > [email protected] > > > Cc: Deucher, Alexander <[email protected]>; Chen, Guchun > > > <[email protected]>; Pan, Xinhui <[email protected]> > > > Subject: RE: [PATCH] drm/amdgpu: add missing cleanups for Polaris12 > > > UVD/VCE on suspend > > > > > > > > > > > > [AMD Official Use Only] > > > > > > > > > > > > If that is done ? > > > > > > > > > > > > + amdgpu_device_ip_set_powergating_state(adev, > > AMD_IP_BLOCK_TYPE_UVD, > > > + > AMD_PG_STATE_GATE); > > > + amdgpu_device_ip_set_clockgating_state(adev, > > AMD_IP_BLOCK_TYPE_UVD, > > > + > > > + AMD_CG_STATE_GATE); > > > > > > > > > > > > Usual order is CG followed by PG. It comes in the else part, so less > likely to > > happen. Nice to fix for code correctness purpose. > > > > > > [Quan, Evan] Thanks Lijo. Make sense to me. However, actually these > code > > were copied from amdgpu_uvd_idle_work_handler() of amdgpu_uvd.c. > > Same logic was used there. So, maybe @Zhu, James or @Liu, Leo can share > > some insights about this. > > > > > > > It looks like it is wrong there as well. We should be gating the clocks > before > > the power. The order is also wrong in amdgpu_uvd_ring_begin_use(). We > > need to ungate the power before the clocks > [Quan, Evan] I created a patch for this. But during the verification, I > got the errors below > [ 87.420822] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, > trying to reset the VCPU!!! > [ 88.443029] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, > trying to reset the VCPU!!! > [ 89.465386] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, > trying to reset the VCPU!!! > [ 90.487629] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, > trying to reset the VCPU!!! > [ 91.510380] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, > trying to reset the VCPU!!! > [ 92.533782] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, > trying to reset the VCPU!!! > [ 93.557400] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, > trying to reset the VCPU!!! > [ 94.580708] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, > trying to reset the VCPU!!! > [ 95.603832] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, > trying to reset the VCPU!!! > [ 96.627727] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, > trying to reset the VCPU!!! > [ 96.657453] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, > giving up!!! > [ 96.665892] [drm:amdgpu_device_ip_set_powergating_state [amdgpu]] > *ERROR* set_powergating_state of IP block <uvd_v6_0> failed -1 > [ 97.697422] amdgpu 0000:02:00.0: [drm:amdgpu_ib_ring_tests [amdgpu]] > *ERROR* IB test failed on uvd (-110). > [ 98.721432] amdgpu 0000:02:00.0: [drm:amdgpu_ib_ring_tests [amdgpu]] > *ERROR* IB test failed on uvd_enc0 (-110). > [ 99.745407] amdgpu 0000:02:00.0: [drm:amdgpu_ib_ring_tests [amdgpu]] > *ERROR* IB test failed on uvd_enc1 (-110). > [ 99.857784] [drm:amdgpu_device_delayed_init_work_handler [amdgpu]] > *ERROR* ib ring test failed (-110). > > After checking the related source code roughly. It seems the underlaying > implementation of -> set_powergating_state(e.g. > uvd_v6_0_set_powergating_state ) performs more jobs than just power gating. > And I guess maybe some of those jobs needs to be performed after -> > set_clockgating_state. James and Leo may comment more. > > BR > Evan > > > > Alex > > > > > > > > > > > > > BR > > > > > > Evan > > > > > > > > > > > > Thanks, > > > > > > Lijo > > > > > > > > > > > > From: Zhu, James <[email protected]> > > > Sent: Thursday, August 19, 2021 7:49 PM > > > To: Quan, Evan <[email protected]>; [email protected] > > > Cc: Deucher, Alexander <[email protected]>; Chen, Guchun > > > <[email protected]>; Lazar, Lijo <[email protected]>; Pan, Xinhui > > > <[email protected]> > > > Subject: Re: [PATCH] drm/amdgpu: add missing cleanups for Polaris12 > > > UVD/VCE on suspend > > > > > > > > > > > > [AMD Official Use Only] > > > > > > > > > > > > > > > > > > Why not move changes into hw_fini? > > > > > > > > > > > > Best Regards! > > > > > > > > > > > > James Zhu > > > > > > ________________________________ > > > > > > From: amd-gfx <[email protected]> on behalf of > > > Evan Quan <[email protected]> > > > Sent: Wednesday, August 18, 2021 11:08 PM > > > To: [email protected] <[email protected]> > > > Cc: Deucher, Alexander <[email protected]>; Chen, Guchun > > > <[email protected]>; Lazar, Lijo <[email protected]>; Quan, Evan > > > <[email protected]>; Pan, Xinhui <[email protected]> > > > Subject: [PATCH] drm/amdgpu: add missing cleanups for Polaris12 > > > UVD/VCE on suspend > > > > > > > > > > > > Perform proper cleanups on UVD/VCE suspend: powergate enablement, > > > clockgating enablement and dpm disablement. This can fix some hangs > > > observed on suspending when UVD/VCE still using(e.g. issue > > > "pm-suspend" when video is still playing). > > > > > > Change-Id: I36f39d9731e0a9638b52d5d92558b0ee9c23a9ed > > > Signed-off-by: Evan Quan <[email protected]> > > > Signed-off-by: xinhui pan <[email protected]> > > > --- > > > drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 24 > > ++++++++++++++++++++++++ > > > drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 23 > > +++++++++++++++++++++++ > > > 2 files changed, 47 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > > > b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > > > index 4eebf973a065..d0fc6ec18c29 100644 > > > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > > > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > > > @@ -554,6 +554,30 @@ static int uvd_v6_0_suspend(void *handle) > > > int r; > > > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > > > > > + /* > > > + * Proper cleanups before halting the HW engine: > > > + * - cancel the delayed idle work > > > + * - enable powergating > > > + * - enable clockgating > > > + * - disable dpm > > > + * > > > + * TODO: to align with the VCN implementation, move the > > > + * jobs for clockgating/powergating/dpm setting to > > > + * ->set_powergating_state(). > > > + */ > > > + cancel_delayed_work_sync(&adev->uvd.idle_work); > > > + > > > + if (adev->pm.dpm_enabled) { > > > + amdgpu_dpm_enable_uvd(adev, false); > > > + } else { > > > + amdgpu_asic_set_uvd_clocks(adev, 0, 0); > > > + /* shutdown the UVD block */ > > > + amdgpu_device_ip_set_powergating_state(adev, > > AMD_IP_BLOCK_TYPE_UVD, > > > + > AMD_PG_STATE_GATE); > > > + amdgpu_device_ip_set_clockgating_state(adev, > > AMD_IP_BLOCK_TYPE_UVD, > > > + > AMD_CG_STATE_GATE); > > > + } > > > + > > > r = uvd_v6_0_hw_fini(adev); > > > if (r) > > > return r; > > > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > > > b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > > > index 6d9108fa22e0..a594ade5d30a 100644 > > > --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > > > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > > > @@ -503,6 +503,29 @@ static int vce_v3_0_suspend(void *handle) > > > int r; > > > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > > > > > + /* > > > + * Proper cleanups before halting the HW engine: > > > + * - cancel the delayed idle work > > > + * - enable powergating > > > + * - enable clockgating > > > + * - disable dpm > > > + * > > > + * TODO: to align with the VCN implementation, move the > > > + * jobs for clockgating/powergating/dpm setting to > > > + * ->set_powergating_state(). > > > + */ > > > + cancel_delayed_work_sync(&adev->vce.idle_work); > > > + > > > + if (adev->pm.dpm_enabled) { > > > + amdgpu_dpm_enable_vce(adev, false); > > > + } else { > > > + amdgpu_asic_set_vce_clocks(adev, 0, 0); > > > + amdgpu_device_ip_set_powergating_state(adev, > > AMD_IP_BLOCK_TYPE_VCE, > > > + > AMD_PG_STATE_GATE); > > > + amdgpu_device_ip_set_clockgating_state(adev, > > AMD_IP_BLOCK_TYPE_VCE, > > > + > AMD_CG_STATE_GATE); > > > + } > > > + > > > r = vce_v3_0_hw_fini(adev); > > > if (r) > > > return r; > > > -- > > > 2.29.0 > > ------------------------------ > > Subject: Digest Footer > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > > ------------------------------ > > End of amd-gfx Digest, Vol 63, Issue 280 > **************************************** >
