[PATCH] drm/amdgpu/display: fix logic regression in dce110 apply_single_controller_ctx_to_hw

[Alex Deucher]

Commit 5de27e1d6755 ("drm/amd/display: Add DP 2.0 SST DC Support")
added a new check for DP 2.0 with a CONFIG_DRM_AMD_DC_DCN check
that removed a bunch of logic if CONFIG_DRM_AMD_DC_DCN was not set,
restore that logic.

Fixes: 5de27e1d6755 ("drm/amd/display: Add DP 2.0 SST DC Support")
Cc: Fangzhi Zuo <jerry....@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c    | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 33743dc2631c..f660472e71fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1545,6 +1545,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
         * function core_link_enable_stream
         */
        if (!(hws->wa.dp_hpo_and_otg_sequence && 
is_dp_128b_132b_signal(pipe_ctx)))
+#endif
                /*  */
                /* Do not touch stream timing on seamless boot optimization. */
                if (!pipe_ctx->stream->apply_seamless_boot_optimization)
@@ -1558,12 +1559,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
        if (pipe_ctx->stream_res.tg->funcs->set_drr)
                pipe_ctx->stream_res.tg->funcs->set_drr(
                        pipe_ctx->stream_res.tg, &params);
-#else
-       /*  */
-       /* Do not touch stream timing on seamless boot optimization. */
-       if (!pipe_ctx->stream->apply_seamless_boot_optimization)
-               hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
-#endif
 
        // DRR should set trigger event to monitor surface update event
        if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
-- 
2.31.1