[PATCH 2/3] amdgpu/pm: insert attempt to call emit_clock_levels into amdgpu_get_pp_od_clk_voltage

[Darren Powell]

  Use new API function emit_clock_levels to display to overclocking values, 
with a fallback
  to the print_clock_levels if the first call fails.

 == Test ==
 LOGFILE=pp_clk.test.log
 AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
 AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print 
$9}'`
 HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}

 lspci -nn | grep "VGA\|Display"  > $LOGFILE
 FILES="pp_od_clk_voltage"

 for f in $FILES
 do
   echo === $f === >> $LOGFILE
   cat $HWMON_DIR/device/$f >> $LOGFILE
 done
 cat $LOGFILE

Signed-off-by: Darren Powell <darren.pow...@amd.com>
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 46 ++++++++++++++++++++++--------
 1 file changed, 34 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index a1169a2397ca..04992a3bc1d2 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -904,8 +904,17 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device 
*dev,
 {
        struct drm_device *ddev = dev_get_drvdata(dev);
        struct amdgpu_device *adev = drm_to_adev(ddev);
-       ssize_t size;
+       int size = 0;
        int ret;
+       enum pp_clock_type od_clocks[6] = {
+               OD_SCLK,
+               OD_MCLK,
+               OD_VDDC_CURVE,
+               OD_RANGE,
+               OD_VDDGFX_OFFSET,
+               OD_CCLK,
+       };
+       uint clk_index;
 
        if (amdgpu_in_reset(adev))
                return -EPERM;
@@ -918,16 +927,29 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device 
*dev,
                return ret;
        }
 
-       if (adev->powerplay.pp_funcs->print_clock_levels) {
-               size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
-               size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
-               size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, 
buf+size);
-               size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, 
buf+size);
-               size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
-               size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf+size);
-       } else {
-               size = sysfs_emit(buf, "\n");
+       ret = -EOPNOTSUPP;
+       if (adev->powerplay.pp_funcs->emit_clock_levels) {
+               ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[0], buf, 
&size);
+       }
+
+       if (ret > 0) {
+               /* Proceed with emit for other od clocks if the first call 
succeeds */
+               for(clk_index = 1 ; clk_index < 6 ; clk_index++)
+                       amdgpu_dpm_emit_clock_levels(adev, 
od_clocks[clk_index], buf, &size);
        }
+       else {
+               if (adev->powerplay.pp_funcs->print_clock_levels) {
+                       size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, 
buf);
+                       size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, 
buf+size);
+                       size += amdgpu_dpm_print_clock_levels(adev, 
OD_VDDC_CURVE, buf+size);
+                       size += amdgpu_dpm_print_clock_levels(adev, 
OD_VDDGFX_OFFSET, buf+size);
+                       size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, 
buf+size);
+                       size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, 
buf+size);
+               } else {
+                       size = sysfs_emit(buf, "\n");
+               }
+       }
+
        pm_runtime_mark_last_busy(ddev->dev);
        pm_runtime_put_autosuspend(ddev->dev);
 
@@ -2075,8 +2097,8 @@ static int default_attr_update(struct amdgpu_device 
*adev, struct amdgpu_device_
        } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
                *states = ATTR_STATE_UNSUPPORTED;
                if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
-                   (is_support_sw_smu(adev) && adev->smu.is_apu) ||
-                       (!is_support_sw_smu(adev) && hwmgr->od_enabled))
+                   (is_support_sw_smu(adev) && adev->smu.is_apu)     ||
+                   (!is_support_sw_smu(adev) && hwmgr->od_enabled)      )
                        *states = ATTR_STATE_SUPPORTED;
        } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
                if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
-- 
2.34.1