On Fri, Jan 7, 2022 at 7:07 AM Tom St Denis <[email protected]> wrote:
>
> The function amdgpu_mm_wreg_mmio_rlc() is used by debugfs to write to
> MMIO registers. It didn't support registers beyond the BAR mapped MMIO
> space. This adds pcie indirect write support.
>
> Signed-off-by: Tom St Denis <[email protected]>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index c38e0e87090b..53a04095a6db 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -552,7 +552,7 @@ void amdgpu_device_wreg(struct amdgpu_device *adev,
> }
>
> /**
> - * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC
> path if in range
> + * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect
> mmio or with RLC path if in range
> *
> * this function is invoked only the debugfs register access
> */
> @@ -567,6 +567,8 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
> adev->gfx.rlc.funcs->is_rlcg_access_range) {
> if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
> return adev->gfx.rlc.funcs->sriov_wreg(adev, reg, v,
> 0, 0);
> + } else if ((reg * 4) >= adev->rmmio_size) {
> + adev->pcie_wreg(adev, reg * 4, v);
Actually, for older asics, we shouldn't we be using mmINDEX/mmDATA
rather than the pcie indirect registers? Or is that handled already
somehow?
Alex
> } else {
> writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
> }
> --
> 2.32.0
>
