[PATCH] drm/amd/display: Shorten delay time to 1us while resetting FIFO

[Liu, Zhan]

[AMD Official Use Only]

[Why]
Current FIFO reset delay for dcn10 is 100us, which is too long
and will fail atomic flip. As a result, there will be no display
on boot.

[How]
Shorten delay time to 1us. This also aligns with FIFO reset delay
on other ASICs.

Signed-off-by: Zhan Liu <zhan....@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index bf4436d7aaab..2077c22befa5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -909,7 +909,7 @@ void enc1_stream_encoder_reset_fifo(

        /* set DIG_START to 0x1 to reset FIFO */
        REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
-       udelay(100);
+       udelay(1);

        /* write 0 to take the FIFO out of reset */
        REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
--
2.25.1