On Fri, Apr 08, 2022 at 05:04:55PM -0400, Alex Deucher wrote:
> Use div_u64() rather than a a 64 bit divide.
>
> Fixes: 3fe5739db48843 ("drm/amd/display: Add flip interval workaround")
> Reported-by: kernel test robot <l...@intel.com>
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> Cc: Angus Wang <angus.w...@amd.com>
> Cc: Anthony Koo <anthony....@amd.com>
> Cc: Aric Cyr <aric....@amd.com>
> Cc: Nathan Chancellor <nat...@kernel.org>
This resolves the build failure for me.
Reviewed-by: Nathan Chancellor <nat...@kernel.org>
> ---
> drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> index 0130f1879116..d2d76ce56f89 100644
> --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> @@ -1239,7 +1239,7 @@ void mod_freesync_handle_v_update(struct mod_freesync
> *mod_freesync,
> if (in_out_vrr->supported == false)
> return;
>
> - cur_timestamp_in_us = dm_get_timestamp(core_freesync->dc->ctx)/10;
> + cur_timestamp_in_us = div_u64(dm_get_timestamp(core_freesync->dc->ctx),
> 10);
>
> in_out_vrr->flip_interval.vsyncs_between_flip++;
> in_out_vrr->flip_interval.v_update_timestamp_in_us =
> cur_timestamp_in_us;
> --
> 2.35.1
>
