Re: [PATCH v2 1/3] Documentation/gpu: Add info table for ASICs

Thu, 11 Aug 2022 12:45:36 -0700 

Hi Kent,

First of all, thanks for your feedback.
See my comments inline.

On 2022-08-11 12:02, Russell, Kent wrote:

[AMD Official Use Only - General]

I noticed that you added DCE and VCE/UVD prefixes in the columns, but not GC or 
SDMA.
E.g.
    CHIP                  DCE      GC             VCE                           
SDMA
  BONAIRE        DCE 8  7        VCE 2 / UVD 4.2        1
Are you referencing when I added it in some specific lines? If so, I added it because we may have a different architecture for the same area. For example, DCE is our old display architecture, and we replaced it with DCN. That's why I added DCE/DCN in the label, and in the ASIC description, I specify if it is a DCE or DCN. 


For consistency, should we drop the DCE/VCE/UVD prefixes and add a separate UVD 
column, so it's just:
Iirc UVD is the previous version of VCE; in that case, I think they should be grouped. Or is UVD a different component? 


    CHIP                  DCE      GC           VCE    UVD      SDMA
  BONAIRE        8      7       VCE 2   4.2     1
? I know that from a compute perspective, I'd like to have the columns 
represent the fields, so there's less to parse through, but I am not a display 
guy so the DCE/VCE/UVD relationship is a mystery to me.

Also, for VG10 you have SDMA 4.0.0, but Polaris it's SDMA 3 . Again, just 
consistency with trailing decimals. I don't know if that's just because we didn't 
do point releases on SDMA <4 or whatnot, but it's something I observed.
I also don't know if we have a good reason for not using the decimal part, but I can add it to all components if it makes sense. Maybe Alex know? 

Thanks
Siqueira



I am not staunchly steadfast one way or another, I just wanted to hear 
rationale for it. Especially if we're maintaining it going forward, and for 
when someone inevitably starts parsing it via automated script and needs 
consistency. If you're confident in the format and can justify it, then that's 
sufficient for me.

  Kent


-----Original Message-----
From: Siqueira, Rodrigo <rodrigo.sique...@amd.com>
Sent: Thursday, August 11, 2022 11:48 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry <harry.wentl...@amd.com>; Kazlauskas, Nicholas
<nicholas.kazlaus...@amd.com>; Lakha, Bhawanpreet
<bhawanpreet.la...@amd.com>; Wu, Hersen <hersenxs...@amd.com>;
Hung, Alex <alex.h...@amd.com>; Pelloux-Prayer, Pierre-Eric <Pierre-
eric.pelloux-pra...@amd.com>; Li, Sun peng (Leo) <sunpeng...@amd.com>;
Simon Ser <cont...@emersion.fr>; Pekka Paalanen
<pekka.paala...@collabora.com>; Sean Paul <seanp...@chromium.org>; Mark
Yacoub <markyac...@chromium.org>; Pierre-Loup
<pgriff...@valvesoftware.com>; Michel Dänzer
<michel.daen...@mailbox.org>; Russell, Kent <kent.russ...@amd.com>
Subject: [PATCH v2 1/3] Documentation/gpu: Add info table for ASICs

Amdgpu driver is used in an extensive range of devices, and each ASIC
has some specific configuration. As a result of this variety, sometimes
it is hard to identify the correct block that might cause the issue.
This commit expands the amdgpu kernel-doc to alleviate this issue by
introducing one ASIC table that describes dGPU and another one that
shares the APU info.

Cc: Harry Wentland <harry.wentl...@amd.com>
Cc: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
Cc: Bhawanpreet Lakha <bhawanpreet.la...@amd.com>
Cc: Hersen Wu <hersenxs...@amd.com>
Cc: Alex Hung <alex.h...@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-pra...@amd.com>
Cc: Leo Li <sunpeng...@amd.com>
Cc: Simon Ser <cont...@emersion.fr>
Cc: Pekka Paalanen <pekka.paala...@collabora.com>
Cc: Sean Paul <seanp...@chromium.org>
Cc: Mark Yacoub <markyac...@chromium.org>
Cc: Pierre-Loup <pgriff...@valvesoftware.com>
Cc: Michel Dänzer <michel.daen...@mailbox.org>
Cc: Kent Russell <kent.russ...@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
---
  .../gpu/amdgpu/apu-asic-info-table.csv        |  8 +++++++
  .../gpu/amdgpu/dgpu-asic-info-table.csv       | 24 +++++++++++++++++++
  Documentation/gpu/amdgpu/driver-misc.rst      | 17 +++++++++++++
  3 files changed, 49 insertions(+)
  create mode 100644 Documentation/gpu/amdgpu/apu-asic-info-table.csv
  create mode 100644 Documentation/gpu/amdgpu/dgpu-asic-info-table.csv

diff --git a/Documentation/gpu/amdgpu/apu-asic-info-table.csv
b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
new file mode 100644
index 000000000000..98c6988e424e
--- /dev/null
+++ b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
@@ -0,0 +1,8 @@
+Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN
version, SDMA version
+Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3
+Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx,
RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0
+Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2
+Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx,
RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1
+SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1
+Ryzen 5000 series, GREEN SARDINE, DCN 2.1, 9.3, VCN 2.2, 4.1.1
+Ryzen 6000 Zen, YELLOW CARP, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3
diff --git a/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
b/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
new file mode 100644
index 000000000000..84617aa35dab
--- /dev/null
+++ b/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
@@ -0,0 +1,24 @@
+Product Name, Code Reference, DCN/DCE version, GC version, VCN version,
SDMA version
+AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series,
HAINAN, --,  6, --, --
+AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, --
+AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND,
DCE 6, 6, VCE 1 / UVD 3, --
+AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN,
DCE 6, 6, VCE 1 / UVD 3, --
+AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M)
/W4100 Series, VERDE, DCE 6, 6, VCE 1 / UVD 3, --
+AMD Radeon HD M280X /M380 /7700 /8950 /W5100, BONAIRE, DCE 8, 7, VCE
2 / UVD 4.2, 1
+AMD Radeon (R9|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE
2 / UVD 4.2, 1
+AMD Radeon (TM) R(5|7) M315 /M340 /M360, TOPAZ, *, 8, --, 2
+AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA,
DCE 10, 8, VCE 3 / UVD 5, 3
+AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3
+Radeon RX 470 /480 /570 /580 /590 Series - AMD Radeon (TM) (Pro WX) 5100
/E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS10, DCE 11.2, 8, VCE 3.4 /
UVD 6.3, 3
+Radeon (TM) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11,
DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
+Radeon (RX/Pro) 500 /540(X) /550 /640 /WX2100 /WX3100 /WX200 Series,
POLARIS12, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
+Radeon (RX|TM) (PRO|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG
MxGPU, VEGA10, DCE 12, 9.0.1, VCE 4.0.0 / UVD 7.0.0, 4.0.0
+AMD Radeon (Pro) VII /MI50 /MI60, VEGA20, DCE 12, 9.4.0, VCE 4.1.0 / UVD
7.2.0, 4.2.0
+MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2
+MI200, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0
+AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN
2.0.0, 10.1.10, VCN 2.0.0, 5.0.0
+AMD Radeon (Pro) 5300 /5500XTB/5500(XT|M) /W5500M /W5500, NAVI14,
DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0.2
+AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0,
10.3.0, VCN 3.0.0, 5.2.0
+AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0,
10.3.2, VCN 3.0.0, 5.2.2
+AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH,
DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4
+AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN
3.0.3, 10.3.5, VCN 3.0.33, 5.2.5
diff --git a/Documentation/gpu/amdgpu/driver-misc.rst
b/Documentation/gpu/amdgpu/driver-misc.rst
index e3d6b2fa2493..1800543d45f7 100644
--- a/Documentation/gpu/amdgpu/driver-misc.rst
+++ b/Documentation/gpu/amdgpu/driver-misc.rst
@@ -32,6 +32,23 @@ unique_id
  .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
     :doc: unique_id

+Accelerated Processing Units (APU) Info
+---------------------------------------
+
+.. csv-table::
+   :header-rows: 1
+   :widths: 3, 2, 2, 1, 1, 1
+   :file: ./apu-asic-info-table.csv
+
+Discrete GPU Info
+-----------------
+
+.. csv-table::
+   :header-rows: 1
+   :widths: 3, 2, 2, 1, 1, 1
+   :file: ./dgpu-asic-info-table.csv
+
+
  GPU Memory Usage Information
  ============================

--
2.35.1

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