From: Dillon Varone <dillon.var...@amd.com>
[WHY?]
In some cases, DCFCLK hardmin requests are not acknowledged by SMU as
the requested clock does not have a compatible ratio with current FCLK,
and it cannot be changed as FCLK P-state is not allowed.
[HOW?]
Allow FCLK p-state change prior to changing DCFCLK hardmin.
Reviewed-by: Alvin Lee <alvin.l...@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahf...@amd.com>
Signed-off-by: Dillon Varone <dillon.var...@amd.com>
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 44 ++++++++++---------
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index f0f3f66629cc..96d5e0d5b3ce 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -333,6 +333,21 @@ static void dcn32_update_clocks(struct clk_mgr
*clk_mgr_base,
if (enter_display_off == safe_to_lower)
dcn30_smu_set_num_of_displays(clk_mgr, display_count);
+ clk_mgr_base->clks.fclk_prev_p_state_change_support =
clk_mgr_base->clks.fclk_p_state_change_support;
+
+ total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc,
context);
+ fclk_p_state_change_support =
new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
+
+ if (should_update_pstate_support(safe_to_lower,
fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
+ clk_mgr_base->clks.fclk_p_state_change_support =
fclk_p_state_change_support;
+
+ /* To enable FCLK P-state switching, send
FCLK_PSTATE_NOTSUPPORTED message to PMFW */
+ if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21
&& clk_mgr_base->clks.fclk_p_state_change_support && update_fclk) {
+ /* Handle the code for sending a message to
PMFW that FCLK P-state change is supported */
+ dcn32_smu_send_fclk_pstate_message(clk_mgr,
FCLK_PSTATE_SUPPORTED);
+ }
+ }
+
if (dc->debug.force_min_dcfclk_mhz > 0)
new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz >
(dc->debug.force_min_dcfclk_mhz * 1000)) ?
new_clocks->dcfclk_khz :
(dc->debug.force_min_dcfclk_mhz * 1000);
@@ -352,7 +367,6 @@ static void dcn32_update_clocks(struct clk_mgr
*clk_mgr_base,
clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
clk_mgr_base->clks.prev_p_state_change_support =
clk_mgr_base->clks.p_state_change_support;
- clk_mgr_base->clks.fclk_prev_p_state_change_support =
clk_mgr_base->clks.fclk_p_state_change_support;
clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
@@ -361,9 +375,8 @@ static void dcn32_update_clocks(struct clk_mgr
*clk_mgr_base,
dcn32_smu_send_cab_for_uclk_message(clk_mgr,
clk_mgr_base->clks.num_ways);
}
- total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc,
context);
+
p_state_change_support = new_clocks->p_state_change_support ||
(total_plane_count == 0);
- fclk_p_state_change_support =
new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
if (should_update_pstate_support(safe_to_lower,
p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
clk_mgr_base->clks.p_state_change_support =
p_state_change_support;
@@ -373,15 +386,14 @@ static void dcn32_update_clocks(struct clk_mgr
*clk_mgr_base,
clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries
- 1].memclk_mhz);
}
- if (should_update_pstate_support(safe_to_lower,
fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&
- clk_mgr_base->ctx->dce_version !=
DCN_VERSION_3_21) {
- clk_mgr_base->clks.fclk_p_state_change_support =
fclk_p_state_change_support;
+ /* Always update saved value, even if new value not set due to
P-State switching unsupported. Also check safe_to_lower for FCLK */
+ if (safe_to_lower &&
(clk_mgr_base->clks.fclk_p_state_change_support !=
clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
+ update_fclk = true;
+ }
- /* To disable FCLK P-state switching, send
FCLK_PSTATE_NOTSUPPORTED message to PMFW */
- if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21
&& !clk_mgr_base->clks.fclk_p_state_change_support) {
- /* Handle code for sending a message to PMFW
that FCLK P-state change is not supported */
- dcn32_smu_send_fclk_pstate_message(clk_mgr,
FCLK_PSTATE_NOTSUPPORTED);
- }
+ if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 &&
!clk_mgr_base->clks.fclk_p_state_change_support && update_fclk) {
+ /* Handle code for sending a message to PMFW that FCLK
P-state change is not supported */
+ dcn32_smu_send_fclk_pstate_message(clk_mgr,
FCLK_PSTATE_NOTSUPPORTED);
}
/* Always update saved value, even if new value not set due to
P-State switching unsupported */
@@ -390,21 +402,11 @@ static void dcn32_update_clocks(struct clk_mgr
*clk_mgr_base,
update_uclk = true;
}
- /* Always update saved value, even if new value not set due to
P-State switching unsupported. Also check safe_to_lower for FCLK */
- if (safe_to_lower &&
(clk_mgr_base->clks.fclk_p_state_change_support !=
clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
- update_fclk = true;
- }
-
/* set UCLK to requested value if P-State switching is
supported, or to re-enable P-State switching */
if (clk_mgr_base->clks.p_state_change_support &&
(update_uclk ||
!clk_mgr_base->clks.prev_p_state_change_support))
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
- if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 &&
clk_mgr_base->clks.fclk_p_state_change_support && update_fclk) {
- /* Handle the code for sending a message to PMFW that
FCLK P-state change is supported */
- dcn32_smu_send_fclk_pstate_message(clk_mgr,
FCLK_PSTATE_SUPPORTED);
- }
-
if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
clk_mgr_base->clks.num_ways >
new_clocks->num_ways) {
clk_mgr_base->clks.num_ways = new_clocks->num_ways;
--
2.37.2
