[AMD Official Use Only - General] Reviewed-by: Tao Zhou <[email protected]>
> -----Original Message----- > From: Chai, Thomas <[email protected]> > Sent: Monday, November 14, 2022 9:52 AM > To: [email protected] > Cc: Chai, Thomas <[email protected]>; Zhang, Hawking > <[email protected]>; Zhou1, Tao <[email protected]>; Li, Candice > <[email protected]>; Chai, Thomas <[email protected]> > Subject: [PATCH] drm/amdgpu: Add umc channel index mapping table for > umc_v8_10 > > Add umc channel index mapping table for umc_v8_10. > > Signed-off-by: YiPeng Chai <[email protected]> > Reviewed-by: Hawking Zhang <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 5 ++++- > drivers/gpu/drm/amd/amdgpu/umc_v8_10.c | 10 ++++++++++ > drivers/gpu/drm/amd/amdgpu/umc_v8_10.h | 4 ++++ > 3 files changed, 18 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c > index 16f52049d986..96e52ec0fb69 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c > @@ -558,7 +558,10 @@ static void gmc_v11_0_set_umc_funcs(struct > amdgpu_device *adev) > adev->umc.node_inst_num = adev->gmc.num_umc; > adev->umc.max_ras_err_cnt_per_query = > UMC_V8_10_TOTAL_CHANNEL_NUM(adev); > adev->umc.channel_offs = > UMC_V8_10_PER_CHANNEL_OFFSET; > - adev->umc.channel_idx_tbl = > &umc_v8_10_channel_idx_tbl[0][0][0]; > + if (adev->umc.node_inst_num == 4) > + adev->umc.channel_idx_tbl = > &umc_v8_10_channel_idx_tbl_ext0[0][0][0]; > + else > + adev->umc.channel_idx_tbl = > &umc_v8_10_channel_idx_tbl[0][0][0]; > adev->umc.ras = &umc_v8_10_ras; > break; > case IP_VERSION(8, 11, 0): > diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c > b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c > index 91235df54e22..b7da4528cf0a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c > +++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c > @@ -45,6 +45,16 @@ const struct channelnum_map_colbit > umc_v8_10_channelnum_map_colbit_table[] = { > {6, 11}, > }; > > +const uint32_t > + umc_v8_10_channel_idx_tbl_ext0[] > + [UMC_V8_10_UMC_INSTANCE_NUM] > + [UMC_V8_10_CHANNEL_INSTANCE_NUM] = { > + {{1, 5}, {7, 3}}, > + {{14, 15}, {13, 12}}, > + {{10, 11}, {9, 8}}, > + {{6, 2}, {0, 4}} > + }; > + > const uint32_t > umc_v8_10_channel_idx_tbl[] > [UMC_V8_10_UMC_INSTANCE_NUM] > diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.h > b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.h > index 849ede88e111..25eaf4af5fcf 100644 > --- a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.h > +++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.h > @@ -66,5 +66,9 @@ extern const uint32_t > [UMC_V8_10_UMC_INSTANCE_NUM] > [UMC_V8_10_CHANNEL_INSTANCE_NUM]; > > +extern const uint32_t > + umc_v8_10_channel_idx_tbl_ext0[] > + [UMC_V8_10_UMC_INSTANCE_NUM] > + [UMC_V8_10_CHANNEL_INSTANCE_NUM]; > #endif > > -- > 2.25.1
