Configure related registers.

Signed-off-by: Tao Zhou <tao.zh...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 66b3f42764df..0bc65b2f0ce8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -862,6 +862,25 @@ static void vcn_v4_0_enable_clock_gating(struct 
amdgpu_device *adev, int inst)
        return;
 }
 
+static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx,
+                               bool indirect)
+{
+       uint32_t tmp;
+
+       tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
+             VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
+             VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
+             VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
+       WREG32_SOC15_DPG_MODE(inst_idx,
+                             SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL),
+                             tmp, 0, indirect);
+
+       tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
+       WREG32_SOC15_DPG_MODE(inst_idx,
+                             SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN),
+                             tmp, 0, indirect);
+}
+
 /**
  * vcn_v4_0_start_dpg_mode - VCN start with dpg mode
  *
@@ -950,6 +969,8 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device 
*adev, int inst_idx, boo
        WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
                VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
 
+       vcn_v4_0_enable_ras(adev, inst_idx, indirect);
+
        /* enable master interrupt */
        WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
                VCN, inst_idx, regUVD_MASTINT_EN),
-- 
2.35.1

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