On Mon, Mar 20, 2023 at 11:58 AM Christian König
<ckoenig.leichtzumer...@gmail.com> wrote:
>
> Am 17.03.23 um 18:17 schrieb Alex Deucher:
> > To provide IP specific shadow sizes. UMDs will use
> > this to query the kernel driver for the size of the
> > shadow buffers.
> >
> > v2: make callback return an int (Alex)
> >
> > Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > index 4ad9e225d6e6..8826f1efc75f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > @@ -219,6 +219,15 @@ struct amdgpu_gfx_ras {
> > struct amdgpu_iv_entry
> > *entry);
> > };
> >
> > +struct amdgpu_gfx_shadow_info {
> > + u32 shadow_size;
> > + u32 shadow_alignment;
> > + u32 csa_size;
> > + u32 csa_alignment;
> > + u32 gds_size;
> > + u32 gds_alignment;
>
> I don't think we need an alignment for those. Otherwise we would run
> into problems with the VA mappings as well.
This is for the GDS save area so it's just memory. The size is just
the amount of GDS on the ASIC and the alignment is standard 256B like
most other CP things.
Alex
>
> Regards,
> Christian.
>
> > +};
> > +
> > struct amdgpu_gfx_funcs {
> > /* get the gpu clock counter */
> > uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
> > @@ -236,6 +245,8 @@ struct amdgpu_gfx_funcs {
> > u32 queue, u32 vmid);
> > void (*init_spm_golden)(struct amdgpu_device *adev);
> > void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
> > + int (*get_gfx_shadow_info)(struct amdgpu_device *adev,
> > + struct amdgpu_gfx_shadow_info
> > *shadow_info);
> > };
> >
> > struct sq_work {
> > @@ -372,6 +383,7 @@ struct amdgpu_gfx {
> > #define amdgpu_gfx_select_se_sh(adev, se, sh, instance)
> > (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
> > #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid)
> > (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
> > #define amdgpu_gfx_init_spm_golden(adev)
> > (adev)->gfx.funcs->init_spm_golden((adev))
> > +#define amdgpu_gfx_get_gfx_shadow_info(adev, si)
> > (adev)->gfx.funcs->get_gfx_shadow_info((adev), (si))
> >
> > /**
> > * amdgpu_gfx_create_bitmask - create a bitmask
>
