From: Lijo Lazar <[email protected]> Add additional XCC programming sequences.
Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 26 +++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 3682b0a64200..7b589f279ece 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1155,6 +1155,29 @@ void gfx_v9_4_3_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) WREG32_SOC15(GC, xcc_id, regCPC_PSP_DEBUG, data); } +static void gfx_v9_4_3_program_xcc_id(struct amdgpu_device *adev, int xcc_id) +{ + uint32_t tmp = 0; + + switch (adev->gfx.num_xcd) { + /* directly config VIRTUAL_XCC_ID to 0 for 1-XCC */ + case 1: + WREG32_SOC15(GC, xcc_id, regCP_HYP_XCP_CTL, 0x8); + break; + case 2: + tmp = (xcc_id % adev->gfx.num_xcc_per_xcp) << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, VIRTUAL_XCC_ID); + tmp = tmp | (adev->gfx.num_xcd << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, NUM_XCC_IN_XCP)); + WREG32_SOC15(GC, xcc_id, regCP_HYP_XCP_CTL, tmp); + + tmp = xcc_id << REG_FIELD_SHIFT(CP_PSP_XCP_CTL, PHYSICAL_XCC_ID); + tmp = tmp | (xcc_id << REG_FIELD_SHIFT(CP_PSP_XCP_CTL, XCC_DIE_ID)); + WREG32_SOC15(GC, xcc_id, regCP_PSP_XCP_CTL, tmp); + break; + default: + break; + } +} + static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) { uint32_t rlc_setting; @@ -1954,6 +1977,9 @@ static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) return r; } + /* set the virtual and physical id based on partition_mode */ + gfx_v9_4_3_program_xcc_id(adev, i); + r = gfx_v9_4_3_kiq_resume(adev, i); if (r) return r; -- 2.39.2
