Log when Channel Equalization is successful,
and DP link training completed.
Cc: Aurabindo Pillai <aurabindo.pil...@amd.com>
Cc: Fangzhi Zuo <jerry....@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmu...@amd.com>
---
v2:
- For consistency of the printed messages, either drop or keep %s for both the
lines - it is dropped (Aurabindo)
- For 128b/132b, moved the statements after EQ interlane alignment
is done.
v3:
- retained %s for both the lines, useful for better debugging
.../display/dc/link/protocols/link_dp_training_128b_132b.c | 3 +++
.../amd/display/dc/link/protocols/link_dp_training_8b_10b.c | 6 +++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
index 23d380f09a21..a1990118cf50 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
@@ -136,6 +136,9 @@ static enum link_training_result
dp_perform_128b_132b_channel_eq_done_sequence(
result = LINK_TRAINING_ABORT;
} else if
(dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b) {
/* pass */
+ DC_LOG_HW_LINK_TRAINING("%s: Channel EQ done.\n",
__func__);
+ DC_LOG_HW_LINK_TRAINING("%s: DP 128b/132b Link Training
successful\n",
+ __func__);
break;
} else if (wait_time >= lt_settings->eq_wait_time_limit) {
result = DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT;
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
index 3889ebb2256b..104da87f395a 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
@@ -339,8 +339,12 @@ enum link_training_result
perform_8b_10b_channel_equalization_sequence(
/* 6. check CHEQ done*/
if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
dp_is_symbol_locked(lane_count,
dpcd_lane_status) &&
-
dp_is_interlane_aligned(dpcd_lane_status_updated))
+
dp_is_interlane_aligned(dpcd_lane_status_updated)) {
+ DC_LOG_HW_LINK_TRAINING("%s: Channel EQ done.\n",
__func__);
+ DC_LOG_HW_LINK_TRAINING("%s: DP 8b/10b Link Training
successful\n",
+ __func__);
return LINK_TRAINING_SUCCESS;
+ }
/* 7. update VS/PE/PC2 in lt_settings*/
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
--
2.25.1
