From: Ilya Bakoulin <ilya.bakou...@amd.com>

[Why]
Some scalers do not pick up color space updates unless the DP link
is disabled/re-enabled which can result in incorrect/washed out
HDR colors in some cases.

[How]
Call set_dpms_on to disable the link, re-train and re-enable with the
updated output color space.

Reviewed-by: Aric Cyr <aric....@amd.com>
Acked-by: Alan Liu <haoping....@amd.com>
Signed-off-by: Ilya Bakoulin <ilya.bakou...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +++++++
 drivers/gpu/drm/amd/display/dc/dc.h      | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1fe040544051..7b68ff0f9c4a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3268,6 +3268,13 @@ static void commit_planes_do_stream_update(struct dc *dc,
                                                dc->hwss.prepare_bandwidth(dc, 
dc->current_state);
                                        
dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);
                                }
+                       } else if 
(pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && 
stream_update->output_color_space
+                                       && !stream->dpms_off && 
dc_is_dp_signal(pipe_ctx->stream->signal)) {
+                               /*
+                                * Workaround for firmware issue in some 
receivers where they don't pick up
+                                * correct output color space unless DP link is 
disabled/re-enabled
+                                */
+                               dc->link_srv->set_dpms_on(dc->current_state, 
pipe_ctx);
                        }
 
                        if (stream_update->abm_level && 
pipe_ctx->stream_res.abm) {
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 4424e7abb801..892e3adb99d9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1506,6 +1506,7 @@ struct dc_link {
                /* Forced DPIA into TBT3 compatibility mode. */
                bool dpia_forced_tbt3_mode;
                bool dongle_mode_timing_override;
+               bool blank_stream_on_ocs_change;
        } wa_flags;
        struct link_mst_stream_allocation_table mst_stream_alloc_table;
 
-- 
2.34.1

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