[Public]
Series is:
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
________________________________
From: Huang, Tim <tim.hu...@amd.com>
Sent: Wednesday, June 7, 2023 4:02 AM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Deucher, Alexander <alexander.deuc...@amd.com>; Zhang, Yifan
<yifan1.zh...@amd.com>; Liu, Aaron <aaron....@amd.com>; Guo, Shikai
<shikai....@amd.com>; Huang, Tim <tim.hu...@amd.com>
Subject: [PATCH 3/3] drm/amd/pm: enable more Pstates profile levels for SMU
v13.0.4
This patch enables following UMD stable Pstates profile
levels for power_dpm_force_performance_level interface.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: Tim Huang <tim.hu...@amd.com>
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 54 ++++++++++++++++++-
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 315a6d8bde2e..ef37dda9908f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -54,6 +54,10 @@
#define FEATURE_MASK(feature) (1ULL << feature)
+#define SMU_13_0_4_UMD_PSTATE_GFXCLK 938
+#define SMU_13_0_4_UMD_PSTATE_SOCCLK 938
+#define SMU_13_0_4_UMD_PSTATE_FCLK 1875
+
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
@@ -908,6 +912,50 @@ static int smu_v13_0_4_force_clk_levels(struct smu_context
*smu,
return ret;
}
+static int smu_v13_0_4_get_dpm_profile_freq(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ enum smu_clk_type clk_type,
+ uint32_t *min_clk,
+ uint32_t *max_clk)
+{
+ int ret = 0;
+ uint32_t clk_limit = 0;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ clk_limit = SMU_13_0_4_UMD_PSTATE_GFXCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK,
&clk_limit, NULL);
+ break;
+ case SMU_SOCCLK:
+ clk_limit = SMU_13_0_4_UMD_PSTATE_SOCCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK,
NULL, &clk_limit);
+ break;
+ case SMU_FCLK:
+ clk_limit = SMU_13_0_4_UMD_PSTATE_FCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK,
&clk_limit, NULL);
+ break;
+ case SMU_VCLK:
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
&clk_limit);
+ break;
+ case SMU_DCLK:
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL,
&clk_limit);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ *min_clk = *max_clk = clk_limit;
+ return ret;
+}
+
static int smu_v13_0_4_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level)
{
@@ -955,7 +1003,11 @@ static int smu_v13_0_4_set_performance_level(struct
smu_context *smu,
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
- /* Temporarily do nothing since the optimal clocks haven't been
provided yet */
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SCLK,
&sclk_min, &sclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_FCLK,
&fclk_min, &fclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SOCCLK,
&socclk_min, &socclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_VCLK,
&vclk_min, &vclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_DCLK,
&dclk_min, &dclk_max);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
--
2.34.1
