[AMD Official Use Only - General] Reviewed-by: Asad Kamal <[email protected]>
-----Original Message----- From: Ma, Le <[email protected]> Sent: Wednesday, July 5, 2023 11:52 AM To: Lazar, Lijo <[email protected]>; [email protected] Cc: Zhang, Hawking <[email protected]>; Deucher, Alexander <[email protected]>; Kamal, Asad <[email protected]>; Gadre, Mangesh <[email protected]> Subject: RE: [PATCH] drm/amdgpu: Remove redundant GFX v9.4.3 sequence [AMD Official Use Only - General] Reviewed-by: Le Ma <[email protected]> > -----Original Message----- > From: Lazar, Lijo <[email protected]> > Sent: Wednesday, July 5, 2023 1:31 PM > To: [email protected] > Cc: Zhang, Hawking <[email protected]>; Deucher, Alexander > <[email protected]>; Kamal, Asad <[email protected]>; Ma, Le > <[email protected]>; Gadre, Mangesh <[email protected]> > Subject: [PATCH] drm/amdgpu: Remove redundant GFX v9.4.3 sequence > > Programming of XCC id is already taken care with partition mode change. > > Signed-off-by: Lijo Lazar <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 29 > ------------------------- > 1 file changed, 29 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c > index 51532d0dd7a7..548b1123f7c6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c > @@ -1034,32 +1034,6 @@ static void > gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_ > WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); > } > > -static void gfx_v9_4_3_xcc_program_xcc_id(struct amdgpu_device *adev, > - int xcc_id) > -{ > - uint32_t tmp = 0; > - int num_xcc; > - > - num_xcc = NUM_XCC(adev->gfx.xcc_mask); > - switch (num_xcc) { > - /* directly config VIRTUAL_XCC_ID to 0 for 1-XCC */ > - case 1: > - WREG32_SOC15(GC, GET_INST(GC, xcc_id), > regCP_HYP_XCP_CTL, 0x8); > - break; > - case 2: > - case 4: > - case 6: > - case 8: > - tmp = (xcc_id % adev->gfx.num_xcc_per_xcp) << > REG_FIELD_SHIFT(CP_HYP_XCP_CTL, VIRTUAL_XCC_ID); > - tmp = tmp | (adev->gfx.num_xcc_per_xcp << > REG_FIELD_SHIFT(CP_HYP_XCP_CTL, NUM_XCC_IN_XCP)); > - WREG32_SOC15(GC, GET_INST(GC, xcc_id), > regCP_HYP_XCP_CTL, tmp); > - > - break; > - default: > - break; > - } > -} > - > static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) { > uint32_t rlc_setting; > @@ -1917,9 +1891,6 @@ static int gfx_v9_4_3_xcc_cp_resume(struct > amdgpu_device *adev, int xcc_id) > return r; > } > > - /* set the virtual and physical id based on partition_mode */ > - gfx_v9_4_3_xcc_program_xcc_id(adev, xcc_id); > - > r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); > if (r) > return r; > -- > 2.25.1
