XCP_CTL register is expected to be programmed by firmware. Under certain conditions FW may not have programmed it correctly. As a workaround, program only when FW has not programmed the right values.
Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 28 ++++++++++--------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index c0855c3769d4..084ba50924e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1037,26 +1037,20 @@ static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_ static void gfx_v9_4_3_xcc_program_xcc_id(struct amdgpu_device *adev, int xcc_id) { - uint32_t tmp = 0; - int num_xcc; + uint32_t expval, regval; + int num_xcc, i; num_xcc = NUM_XCC(adev->gfx.xcc_mask); - switch (num_xcc) { - /* directly config VIRTUAL_XCC_ID to 0 for 1-XCC */ - case 1: - WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HYP_XCP_CTL, 0x8); - break; - case 2: - case 4: - case 6: - case 8: - tmp = (xcc_id % adev->gfx.num_xcc_per_xcp) << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, VIRTUAL_XCC_ID); - tmp = tmp | (adev->gfx.num_xcc_per_xcp << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, NUM_XCC_IN_XCP)); - WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HYP_XCP_CTL, tmp); + for (i = 0; i < num_xcc; i++) { + expval = REG_SET_FIELD(expval, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, + adev->gfx.num_xcc_per_xcp); + expval = REG_SET_FIELD(expval, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, + i % adev->gfx.num_xcc_per_xcp); - break; - default: - break; + regval = RREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL); + if (regval != expval) + WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, + expval); } } -- 2.25.1
