Hi all, I'm trying to use the watchdog timer on an ATMega324P for power saving by sleeping for 8 seconds, and then having the watchdog wake the device. However, I'm struggling to set the prescaler flags in WDTCSR.
According to the datasheet, the 'Change Enable' flag (WDCE) must be set to change the prescaler bits, but this clears after 4 clock cycles*. I'm thinking that perhaps, this can't be done in forth because changing the bits will take more than 4 clock cycles (I don't know, I'm guessing). Has anyone done this before and have a solution? If not, I guess I have to write the word in assembler, which I haven't done before. Any pointers on how to do this? Many thanks for any help, David Wallis * From datasheet: • Bit 4 - WDCE: Watchdog Change Enable This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set. Once written to one, hardware will clear WDCE after four clock cycles. ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60134071&iu=/4140/ostg.clktrk _______________________________________________ Amforth-devel mailing list for http://amforth.sf.net/ Amforth-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/amforth-devel
