ok, understood. Thank you !
So the optimized routine would be
do_spirw:
out_ SPDR, tosl
do_spirw1:
in_ temp0, SPSR
sbrs temp0, 7
rjmp do_spirw1 ; wait until complete
in_ tosl, SPDR
ret
Greetings
Rafael
El Viernes 29 de agosto de 2014 19:37, Matthias Trute <[email protected]> escribió:
Hi Rafael,
> do_spirw:
> 1. out_ SPDR, tosl
> do_spirw1:
> 2. in_ temp0, SPSR
> 3. cbr temp0,7
> 4. out_ SPSR, temp0
> 5. in_ temp0, SPSR
> 6. sbrs temp0, 7
> 7. rjmp do_spirw1 ; wait until complete
> 8. in_ tosl, SPDR
> 9. ret
>
> In 1) we transmit a byte (and activate sthe SPI clock). Ok.
> In 2) we read the status register, so far so good
> In 3) we clear thr 3 least significant bits of ths status just read Why ?
> In 4) we write the status register with the just modified byte. Why ?
> In 5) we again read the stats register. Why ?
> &) to 9) is usual stuff
>
> I don't really understand the purpose of the sequence given by steps 2 to 5.
You are probably right, steps 2, 3 and 4 may be simply a waste of cpu
cycles. The SPSR bit 7 is readonly, writing to it is essentially a
NO-Operation. step 5 is necessary however to make step 6 working.
> Another issue
>
> This code does a busy poll. I was wondering if it should instead call PAUSE
> instead
> Two reasons that I can think of:
>
> 1) SPI is a high speed interface. Using PAUSE would degrade performance for
> the highest clock rates.
> 2) We can't invoke PAUSE from inside this assembler word.
>
> Which is the correct assumption ?
Both are right. btw: an interrupt triggered SPI transfer is *not*
necessarily faster than the polled one implemented in n-spi.asm. I've
seen some fantastic postings via google and friends that discussed this
topic.
Matthias
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