*FPGA Engineer - Hillsboro, OR*
*Only USC & GC* *Job Description:-* · Strong FPGA(Altera) design skill, find and fix hardware implementation bottlenecks, timing closure, latency etc. · Capable of functional and architectural definition, floor-planning, simulation, implementation and verification of complex FPGA devices comprising a mix of custom RTL with hard and soft vendor IP cores. · Work at entire architecture, system level, integrate modules and components while maintaining overall system performance and targets · Proficiency with RTL coding using System Verilog, Verilog/VHDL and in all phases of FPGA development including automated self-checking test benches · Experience with high speed digital bus interfaces, such as PCIe, USB, DDR3/4, LPDDR3/4 and working knowledge of digital control interfaces such as SPI, I2C etc. · xperience with scripting languages such as Tcl, Perl, and Python. *Thanks & Regards * *Ashish Gautam* *ashish04.sysm...@gmail.com <ashish04.sysm...@gmail.com>* -- You received this message because you are subscribed to the Google Groups "Android Developers" group. To unsubscribe from this group and stop receiving emails from it, send an email to android-developers+unsubscr...@googlegroups.com. To post to this group, send email to android-developers@googlegroups.com. Visit this group at https://groups.google.com/group/android-developers. To view this discussion on the web visit https://groups.google.com/d/msgid/android-developers/CAD2-NzpGFoRCbZ9%3DCvv%3D3Rdxi%3DM%3DtB9z%3DGb_uej4V2jGtg8ysQ%40mail.gmail.com. For more options, visit https://groups.google.com/d/optout.
