Hello all,
I am currently trying to build a kernel for the Sony Ericsson Xperia
Play (verizon version) off of the source code that overclocks.
I am using Android-NDK v5b (it's the only one that I was able to build
the kernel from source with no errors with) (arm-eabi 4.4.0)
The only error that has me stumped so far is when cross compiling, is
Code:
arch/arm/mach-msm/acpuclock-7x30.c:166: error: initialization makes
integer from pointer without a cast
arch/arm/mach-msm/acpuclock-7x30.c:167: error: initialization makes
integer from pointer without a cast
arch/arm/mach-msm/acpuclock-7x30.c:168: error: initialization makes
integer from pointer without a cast
arch/arm/mach-msm/acpuclock-7x30.c:169: error: initialization makes
integer from pointer without a cast
arch/arm/mach-msm/acpuclock-7x30.c:170: error: initialization makes
integer from pointer without a cast
arch/arm/mach-msm/acpuclock-7x30.c:171: error: initialization makes
integer from pointer without a cast
arch/arm/mach-msm/acpuclock-7x30.c:172: error: initialization makes
integer from pointer without a cast
arch/arm/mach-msm/acpuclock-7x30.c:173: error: initialization makes
integer from pointer without a cast
arch/arm/mach-msm/acpuclock-7x30.c:174: error: initialization makes
integer from pointer without a cast
arch/arm/mach-msm/acpuclock-7x30.c:175: error: initialization makes
integer from pointer without a cast
arch/arm/mach-msm/acpuclock-7x30.c:176: error: initialization makes
integer from pointer without a cast
arch/arm/mach-msm/acpuclock-7x30.c:177: error: initialization makes
integer from pointer without a cast
That points to this (in acpuclock-7x30.c)
Code:
static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 0, 24576, SRC_LPXO, 0, 0, 30720000, 900, VDD_RAW(900) },
{ 0, 61440, PLL_3, 5, 11, 61440000, 900, VDD_RAW(900) },
{ 1, 122880, PLL_3, 5, 5, 61440000, 900, VDD_RAW(900) },
{ 0, 184320, PLL_3, 5, 4, 61440000, 900, VDD_RAW(900) },
/*{ MAX_AXI_KHZ, SRC_AXI, 1, 0, 61440000, 900, VDD_RAW(900) },*/
{ 1, 245760, PLL_3, 5, 2, 61440000, 900, VDD_RAW(900) },
{ 1, 368640, PLL_3, 5, 1, 122800000, 900, VDD_RAW(900) },
{ 1, 460800, PLL_1, 2, 0, 153600000, 950, VDD_RAW(950) },
{ 1, 576000, PLL_1, 2, 0, 153600000, 1000, VDD_RAW(1000) },
{ 1, 652800, PLL_1, 2, 0, 153600000, 1050, VDD_RAW(1050) },
/* AXI has MSMC1 implications. See above. */
{ 1, 768000, PLL_1, 2, 0, 153600000, 1050, VDD_RAW(1050) },
/*
* AXI has MSMC1 implications. See above.
* 806.4MHz is increased to match the SoC's capabilities at runtime
*/
{ 1, 806400, PLL_2, 3, 0, UINT_MAX, 1100, VDD_RAW(1100), &
pll2_tbl[0]},
{ 1, 921600, PLL_2, 3, 0, UINT_MAX, 1150, VDD_RAW(1150), &
pll2_tbl[1]},
{ 1, 1024000, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &
pll2_tbl[2]},
{ 1, 1113000, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &
pll2_tbl[3]},
{ 1, 1200000, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &
pll2_tbl[4]},
{ 1, 1305600, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &
pll2_tbl[5]},
{ 1, 1401600, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &
pll2_tbl[6]},
{ 1, 1516800, PLL_2, 3, 0, UINT_MAX, 1300, VDD_RAW(1300), &
pll2_tbl[7]},
{ 1, 1612800, PLL_2, 3, 0, UINT_MAX, 1300, VDD_RAW(1300), &
pll2_tbl[8]},
{ 1, 1708800, PLL_2, 3, 0, UINT_MAX, 1350, VDD_RAW(1350), &
pll2_tbl[9]},
{ 1, 1804800, PLL_2, 3, 0, UINT_MAX, 1400, VDD_RAW(1400), &
pll2_tbl[10]},
{ 1, 1900800, PLL_2, 3, 0, UINT_MAX, 1475, VDD_RAW(1475), &
pll2_tbl[11]},
{ 1, 2016000, PLL_2, 3, 0, UINT_MAX, 1475, VDD_RAW(1475), &
pll2_tbl[12]},
{ 0 }
};
which in turn points to this:
Code:
static struct pll pll2_tbl[] =
{
{ 42, 0, 1, 0 }, /* 806 MHZ */
{ 48, 1, 3, 0 }, /* 921 MHz */
{ 53, 1, 3, 0 }, /* 1024 MHz */
{ 58, 1, 3, 0 }, /* 1113 MHz */
{ 63, 1, 3, 0 }, /* 1200 MHz */
{ 68, 1, 3, 0 }, /* 1305 MHz */
{ 73, 1, 3, 0 }, /* 1401 MHz */
{ 78, 1, 3, 0 }, /* 1516 MHz */
{ 83, 1, 3, 0 }, /* 1612 MHz */
{ 88, 1, 3, 0 }, /* 1708 MHz */
{ 93, 1, 3, 0 }, /* 1804 MHz */
{ 98, 1, 3, 0 }, /* 1900 MHz */
{ 103, 1, 3, 0 }, /* 2016 MHz */
};
Any pointers you can give me would be very much appreciated
Thank you,
Pax
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