I am not sure whether this is the right place for ART questions. I am trying to add a new optimization pass in ART compiler. There is a problem in creating new temp vreg. Please see below example. SSA form: stmt1: v1_1 = iget a; stmt2: v1_2 = iget b; stmt3: v2_1 = v1_1 + 2; // a + 2
I want to transform above dex code to following: Non-SSA form: stmt1: v3 = iget a; // create new vreg 'v3'. stmt2: v1 = iget b; stmt3: v2 = v3 + 2; // update use of v1_1 with v3; ART compiler has function named GetNewCompilerTemp() for creating temp virtual register. It creates new vreg with negative reg number which is not handled by SSA conversion pass. Also it is not permit to access some bitvector with this new vreg, since it is negative. After transformation, stmt3.vB = negative value. This could not pass the forward process. Question 1, anyone could tell me how to fix this issue? Also, I write a function to crate new temp vreg which has positive reg number by "num_dalvik_registers++". ART now think the dalvik register number is fixed and the incoming argument vregs have the big register number. By this method, vreg layout is changed. Question 2, Is this method feasible? Should I do some change in runtime to make it compatible to the new vreg layout? -- -- unsubscribe: [email protected] website: http://groups.google.com/group/android-porting --- You received this message because you are subscribed to the Google Groups "android-porting" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
