Update of /cvsroot/arcem/arcem
In directory vz-cvs-4.sog:/tmp/cvs-serv17595
Modified Files:
armemu.c c99.h eventq.h
Log Message:
Enormous-looking set of changes that do nothing. Just avoid requiring
a C99 compiler. Would you believe Microsoft Visual Studio 2010 is still
not a C99 compiler. So we fake it where we can, but the main problem is
that you require C99 to be able to do inline declarations. So the bulk
of this huge ugly commit is just changing the scope of declaration of
variables.
I've done as much as I can to test I've not broken things, on Linux and
Windows VS2010 builds. It's possible there's breakage with other platforms
but those are the two I've got to hand to test just now anyway.
Index: armemu.c
===================================================================
RCS file: /cvsroot/arcem/arcem/armemu.c,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -d -r1.17 -r1.18
--- armemu.c 12 May 2012 17:34:51 -0000 1.17
+++ armemu.c 21 Jul 2012 01:01:11 -0000 1.18
@@ -41,13 +41,15 @@
static inline void
ARMul_LoadInstr(ARMul_State *state,ARMword addr, PipelineEntry *p)
{
+ FastMapEntry *entry;
+ FastMapRes res;
state->NumCycles++;
addr &= 0x3fffffc;
ARMul_CLEARABORT;
- FastMapEntry *entry = FastMap_GetEntryNoWrap(state,addr);
- FastMapRes res = FastMap_DecodeRead(entry,state->FastMapMode);
+ entry = FastMap_GetEntryNoWrap(state,addr);
+ res = FastMap_DecodeRead(entry,state->FastMapMode);
// fprintf(stderr,"LoadInstr: %08x maps to entry %08x res %08x (mode %08x pc
%08x)\n",addr,entry,res,MEMC.FastMapMode,state->Reg[15]);
if(FASTMAP_RESULT_DIRECT(res))
{
@@ -89,6 +91,9 @@
static void
ARMul_LoadInstrTriplet(ARMul_State *state,ARMword addr,PipelineEntry *p)
{
+ FastMapEntry *entry;
+ FastMapRes res;
+
if (((uint32_t) (addr << 20)) > 0xff000000) {
ARMul_LoadInstr(state,addr,p);
ARMul_LoadInstr(state,addr+4,p+1);
@@ -101,8 +106,8 @@
ARMul_CLEARABORT;
- FastMapEntry *entry = FastMap_GetEntryNoWrap(state,addr);
- FastMapRes res = FastMap_DecodeRead(entry,state->FastMapMode);
+ entry = FastMap_GetEntryNoWrap(state,addr);
+ res = FastMap_DecodeRead(entry,state->FastMapMode);
if(FASTMAP_RESULT_DIRECT(res))
{
ARMword *data = FastMap_Log2Phy(entry,addr);
@@ -221,69 +226,73 @@
static ARMword RHSFunc_LSL_Imm(ARMul_State *state,ARMword instr,ARMword base)
{
- base = state->Reg[base];
ARMword shamt = BITS(7,11);
+ base = state->Reg[base];
return base<<shamt;
}
static ARMword RHSFunc_LSR_Imm(ARMul_State *state,ARMword instr,ARMword base)
{
- base = state->Reg[base];
ARMword shamt = BITS(7,11);
+ base = state->Reg[base];
return (shamt?base>>shamt:0);
}
static ARMword RHSFunc_ASR_Imm(ARMul_State *state,ARMword instr,ARMword base)
{
- base = state->Reg[base];
ARMword shamt = BITS(7,11);
+ base = state->Reg[base];
return
(shamt?((ARMword)((int32_t)base>>(int)shamt)):((ARMword)((int32_t)base>>31L)));
}
static ARMword RHSFunc_ROR_Imm(ARMul_State *state,ARMword instr,ARMword base)
{
- base = state->Reg[base];
ARMword shamt = BITS(7,11);
+ base = state->Reg[base];
return (shamt?((base << (32 - shamt)) | (base >> shamt)):((base >> 1) |
(CFLAG << 31)));
}
static ARMword RHSFunc_LSL_Reg(ARMul_State *state,ARMword instr,ARMword base)
{
+ ARMword shamt;
UNDEF_Shift;
INCPC;
base = state->Reg[base];
ARMul_Icycles(state,1);
- ARMword shamt = state->Reg[BITS(8,11)] & 0xff;
+ shamt = state->Reg[BITS(8,11)] & 0xff;
return (shamt>=32?0:base<<shamt);
}
static ARMword RHSFunc_LSR_Reg(ARMul_State *state,ARMword instr,ARMword base)
{
+ ARMword shamt;
UNDEF_Shift;
INCPC;
base = state->Reg[base];
ARMul_Icycles(state,1);
- ARMword shamt = state->Reg[BITS(8,11)] & 0xff;
+ shamt = state->Reg[BITS(8,11)] & 0xff;
return (shamt>=32?0:base>>shamt);
}
static ARMword RHSFunc_ASR_Reg(ARMul_State *state,ARMword instr,ARMword base)
{
+ ARMword shamt;
UNDEF_Shift;
INCPC;
base = state->Reg[base];
ARMul_Icycles(state,1);
- ARMword shamt = state->Reg[BITS(8,11)] & 0xff;
+ shamt = state->Reg[BITS(8,11)] & 0xff;
return
(shamt<32?((ARMword)((int32_t)base>>(int)shamt)):((ARMword)((int32_t)base>>31L)));
}
static ARMword RHSFunc_ROR_Reg(ARMul_State *state,ARMword instr,ARMword base)
{
+ ARMword shamt;
UNDEF_Shift;
INCPC;
base = state->Reg[base];
ARMul_Icycles(state,1);
- ARMword shamt = state->Reg[BITS(8,11)] & 0x1f;
+ shamt = state->Reg[BITS(8,11)] & 0x1f;
return ((base << (32 - shamt)) | (base >> shamt));
}
@@ -645,11 +654,12 @@
FastMapRes res = FastMap_DecodeRead(entry,state->FastMapMode);
if(FASTMAP_RESULT_DIRECT(res))
{
+ ARMword *data, count;
/* Do it fast
This assumes we don't differentiate between N & S cycles */
ARMul_CLEARABORT;
- ARMword *data = FastMap_Log2Phy(entry,address&~3);
- ARMword count=0;
+ data = FastMap_Log2Phy(entry,address&~3);
+ count=0;
for(temp=0;temp<16;temp++)
if(BIT(temp))
{
@@ -735,11 +745,12 @@
FastMapRes res = FastMap_DecodeRead(entry,state->FastMapMode);
if(FASTMAP_RESULT_DIRECT(res))
{
+ ARMword *data, count;
/* Do it fast
This assumes we don't differentiate between N & S cycles */
ARMul_CLEARABORT;
- ARMword *data = FastMap_Log2Phy(entry,address&~3);
- ARMword count=0;
+ data = FastMap_Log2Phy(entry,address&~3);
+ count=0;
for(temp=0;temp<16;temp++)
if(BIT(temp))
{
@@ -823,12 +834,14 @@
FastMapRes res = FastMap_DecodeWrite(entry,state->FastMapMode);
if(FASTMAP_RESULT_DIRECT(res))
{
+ ARMword *data, count;
+ ARMEmuFunc *pfunc;
/* Do it fast
This assumes we don't differentiate between N & S cycles */
ARMul_CLEARABORT;
- ARMword *data = FastMap_Log2Phy(entry,address&~3);
- ARMEmuFunc *pfunc = FastMap_Phy2Func(state,data);
- ARMword count=1;
+ data = FastMap_Log2Phy(entry,address&~3);
+ pfunc = FastMap_Phy2Func(state,data);
+ count=1;
*(data++) = state->Reg[temp++];
*(pfunc++) = FASTMAP_CLOBBEREDFUNC;
if (BIT(21) && LHSReg != 15)
@@ -910,12 +923,14 @@
FastMapRes res = FastMap_DecodeWrite(entry,state->FastMapMode);
if(FASTMAP_RESULT_DIRECT(res))
{
+ ARMword *data, count;
+ ARMEmuFunc *pfunc;
/* Do it fast
This assumes we don't differentiate between N & S cycles */
ARMul_CLEARABORT;
- ARMword *data = FastMap_Log2Phy(entry,address&~3);
- ARMEmuFunc *pfunc = FastMap_Phy2Func(state,data);
- ARMword count=1;
+ data = FastMap_Log2Phy(entry,address&~3);
+ pfunc = FastMap_Phy2Func(state,data);
+ count=1;
*(data++) = state->Reg[temp++];
*(pfunc++) = FASTMAP_CLOBBEREDFUNC;
if (BIT(21) && LHSReg != 15)
@@ -987,13 +1002,15 @@
void EmuRate_Update(ARMul_State *state)
{
+ uint64_t iocrate;
+ clock_t nowtime, timediff;
CycleCount nowcycle = ARMul_Time;
CycleDiff cycles = nowcycle-EmuRate_LastUpdateCycle;
/* Ignore if not much time has passed */
if(cycles < 40000)
return;
- clock_t nowtime = clock();
- clock_t timediff = nowtime-EmuRate_LastUpdateTime;
+ nowtime = clock();
+ timediff = nowtime-EmuRate_LastUpdateTime;
if(timediff < 10)
return;
@@ -1009,18 +1026,21 @@
/* Force 8MHz when profiling is on */
ARMul_EmuRate = 8000000;
#else
+ {
uint32_t newrate = (uint32_t) ((((double)cycles)*CLOCKS_PER_SEC)/timediff);
/* Clamp to a sensible minimum value, just in case something crazy happens */
if(newrate < 1000000)
newrate = 1000000;
/* Smooth the value a bit, in case of sudden jumps, and to cope with systems
with poor clock() granularity */
ARMul_EmuRate = (ARMul_EmuRate*3+newrate)>>2;
+ }
#endif
/* Recalculate IOC rates */
+ iocrate = (((uint64_t) 2000000)<<16)/ARMul_EmuRate;
ioc.InvIOCRate = (((uint64_t) ARMul_EmuRate)<<16)/2000000;
- ioc.IOCRate = (((uint64_t) 2000000)<<16)/ARMul_EmuRate;
+ ioc.IOCRate = (uint32_t) iocrate;
/* Update IOC timers again, to ensure the next interrupt occurs at the right
time */
UpdateTimerRegisters(state);
@@ -1194,6 +1214,8 @@
}
#else
/* pipeidx = 0 */
+ CycleCount local_time;
+ ARMword excep, instr;
ARMword r15 = state->Reg[15];
Prof_Begin("Fetch/decode");
switch (state->NextInstr) {
@@ -1208,7 +1230,7 @@
}
Prof_End("Fetch/decode");
- CycleCount local_time = ARMul_Time;
+ local_time = ARMul_Time;
while(((CycleDiff) (local_time-state->EventQ[0].Time)) >= 0)
{
EventQ_Func func = state->EventQ[0].Func;
@@ -1217,7 +1239,7 @@
Prof_EndFunc(func);
}
- ARMword excep = state->Exception &~r15;
+ excep = state->Exception &~r15;
/* Write back updated PC before handling exception/instruction */
state->Reg[15] = r15;
@@ -1236,7 +1258,7 @@
break;
}
- ARMword instr = pipe[1].instr;
+ instr = pipe[1].instr;
if(ARMul_CCCheck(instr,(r15 & CCBITS)))
{
Prof_BeginFunc(pipe[1].func);
Index: c99.h
===================================================================
RCS file: /cvsroot/arcem/arcem/c99.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- c99.h 12 May 2012 17:34:51 -0000 1.3
+++ c99.h 21 Jul 2012 01:01:11 -0000 1.4
@@ -16,6 +16,14 @@
/* For now, assume we're using a C99 compiler */
#include <stdint.h>
+
+#ifdef _MSC_VER
+#define inline __inline
+typedef unsigned char bool;
+#define true 1
+#define false 0
+#else
#include <stdbool.h>
+#endif
#endif
Index: eventq.h
===================================================================
RCS file: /cvsroot/arcem/arcem/eventq.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- eventq.h 12 May 2012 17:34:51 -0000 1.3
+++ eventq.h 21 Jul 2012 01:01:11 -0000 1.4
@@ -40,12 +40,12 @@
/* Reschedule an arbitrary entry, returns new index */
static inline int EventQ_Reschedule(ARMul_State *state,CycleCount
eventtime,EventQ_Func func,int idx)
{
+ int top = state->NumEvents-1;
while((idx > 0) && (((CycleDiff) (state->EventQ[idx-1].Time-eventtime))
> 0))
{
state->EventQ[idx] = state->EventQ[idx-1];
idx--;
}
- int top = state->NumEvents-1;
while((idx < top) && (((CycleDiff)
(state->EventQ[idx+1].Time-eventtime)) < 0))
{
state->EventQ[idx] = state->EventQ[idx+1];
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