On Nov 25, 2017, at 23:14, Luke Kenneth Casson Leighton <[email protected]> wrote: > > ok so this is after flood-fill, remember that GND wires (blue) which > are within tthe GND flood-fill (grey) *are* part of the GND plane, > PADS just continues to highlight their existence (unnecessarily). > > so this gives a clear idea of how the current (arbitrarily-created) > tapers look like. there are no tapers and no keepout areas on layer > 1, because the clearance to... "stuff" is unavoidably within 5-7mil > anyway.
Thanks for the pictures. At the north side of the ESD it looks like something violates the board-level 5mil Cu-Cu clearance but I'm guessing it is actually stray silk screen that just happens to be rendered in the same shade of gray. _______________________________________________ arm-netbook mailing list [email protected] http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to [email protected]
