Richard can you please edit community_ideas micrideksoo oage rhuombustech
maintain all of this there revisioons to revisions of email knoen to be not
a sustainable way to track detailed important information

On Wednesday, July 18, 2018, Richard Wilbur <richard.wil...@gmail.com>
wrote:

> Addendum
>
> Why?
> 1.  Make VESA DDC lines conform to VESA DDC spec. (VDD=5.0V, I2C
> signalling)[1]
> 2.  Respect VREFTTL in the range of 3.3-5.0V on EOMA side of VESA DDC
> lines.
> 3.  Respect EOMA requirement that all lines except EOMA I2C be tri-stated
> at power on.
>
> How?
> 1.  Connect pull-up resistors for VESA_SDA(R8) and VESA_SCL(R12) to
> VESA_PWR (+5.0V) instead of VREFTTL.  Maximum current requirement on
> VESA_PWR is ~670uA.
> 2.  Implement circuit in attached
> diagram[EOMA_I2C_circuit_sketch_small.png] on each of SDA and SCL.  I have
> attached a spreadsheet[EOMA_I2C_VESA_calc.pdf] showing how this
> accommodates the I2C signalling for VDD=3.3V=VREFTTL and VDD=5.0V.[2]  It
> also accommodates the EOMA68 VREFTTL input levels by not allowing the EOMA
> side of the signal to exceed one Schottky diode drop(0.3V) above VDD=3.3V.
> 3.  Enable the current limiting regulator (SY6280) for VESA_PWR (+5.0V on
> VGA pin 9) with latch of LCDDE when it first goes active (line coming from
> EOMA68 connector).
>
> References:
>
> [1] https://en.wikipedia.org/wiki/Display_Data_Channel
> [2] http://www.nxp.com/documents/user_manual/UM10204.pdf
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