On Sun, Oct 22, 2017 at 10:48:51PM -0700, Stephen Graf wrote:
> Yes, the latest diff from Patrick solves the system crash. In addition to
> the driver changes, syscon must be made to start before dwxe and somewhere
> the noisolate flag must be set. I set the noisolate flag in the ukphy
> driver, but I am not sure that is the correct place. Can it be done in dwxe
> and somehow sent to the phy?
It is a flag to mii_attach() Though it should probably be limited
to when the internal phy is used.
Index: if_dwxe.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/if_dwxe.c,v
retrieving revision 1.3
diff -u -p -r1.3 if_dwxe.c
--- if_dwxe.c 1 Oct 2017 06:42:43 -0000 1.3
+++ if_dwxe.c 23 Oct 2017 05:55:09 -0000
@@ -425,7 +425,7 @@ dwxe_attach(struct device *parent, struc
dwxe_reset(sc);
mii_attach(self, &sc->sc_mii, 0xffffffff, phyloc,
- MII_OFFSET_ANY, 0);
+ MII_OFFSET_ANY, MIIF_NOISOLATE);
if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
printf("%s: no PHY found!\n", sc->sc_dev.dv_xname);
ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
>
> The dtb that I am using has the following:
>
> ethernet@1c30000 {
> compatible = "allwinner,sun8i-h3-emac";
> syscon = <0x6>;
> reg = <0x1c30000 0x104>;
> reg-names = "emac";
> interrupts = <0x0 0x52 0x4>;
> resets = <0x2 0xc>, <0x2 0x27>;
> reset-names = "ahb", "ephy";
> clocks = <0x2 0x1b>, <0x2 0x43>;
> clock-names = "ahb", "ephy";
> pinctrl-names = "default";
> pinctrl-0 = <0x48>;
> #address-cells = <0x1>;
> #size-cells = <0x0>;
> status = "okay";
> phy-handle = <0x47>;
> phy-mode = "mii";
> allwinner,leds-active-low;
> phandle = <0x31>;
>
>
> ethernet-phy@1 {
> reg = <0x1>;
> phandle = <0x47>;
> };
> };
>
>
> syscon@1c00000 {
> compatible = "allwinner,sun8i-h3-system-controller",
> "syscon";
> reg = <0x1c00000 0x1000>;
> reg-names = "syscon";
> phandle = <0x6>;
> };
>
> This is the change from ver 1.3.
>
> # diff /backup/src_backup_2017-10-22/if_dwxe.c
> /usr/src/sys/dev/fdt/if_dwxe.c
> 149,153c149,153
> < #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_MASK (0x7 << 20)
> < #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_16 (0 << 20)
> < #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_32 (1 << 20)
> < #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_64 (2 << 20)
> < #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_128 (3 << 20)
> ---
> > #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_MASK 0x7
> > #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_16 0
> > #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_32 1
> > #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_64 2
> > #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_128 3
> 238a239
> > #define SYSCON_H3_EPHY_ADDR_MASK 0x1f
> 272a274
> > int sc_phyloc;
> 360d361
> < int phyloc = MII_PHY_ANY;
> 375,376c376
> < phyloc = OF_getpropint(node, "reg", phyloc);
> <
> ---
> > sc->sc_phyloc = OF_getpropint(node, "reg", MII_PHY_ANY);
> 380,381c380,381
> < clock_enable(faa->fa_node, "stmmaceth");
> < reset_deassert(faa->fa_node, "stmmaceth");
> ---
> > clock_enable_all(faa->fa_node);
> > reset_deassert_all(faa->fa_node);
> 389c389
> < sc->sc_clk = clock_get_frequency(faa->fa_node, "stmmaceth");
> ---
> > sc->sc_clk = clock_get_frequency(faa->fa_node, "ahb");
> 427c427
> < mii_attach(self, &sc->sc_mii, 0xffffffff, phyloc,
> ---
> > mii_attach(self, &sc->sc_mii, 0xffffffff, sc->sc_phyloc,
> 469,470c469,476
> < panic("%s: setup internal phy", DEVNAME(sc));
> < return;
> ---
> > syscon &= ~SYSCON_H3_EPHY_SHUTDOWN;
> > syscon |= SYSCON_H3_EPHY_SELECT|SYSCON_H3_EPHY_CLK_SEL;
> > if (OF_getproplen(sc->sc_node,
> "allwinner,leds-active-low") >= 0)
> > syscon |= SYSCON_H3_EPHY_LED_POL;
> > else
> > syscon &= ~SYSCON_H3_EPHY_LED_POL;
> > syscon &= ~(SYSCON_H3_EPHY_ADDR_MASK <<
> SYSCON_H3_EPHY_ADDR_SHIFT);
> > syscon |= sc->sc_phyloc << SYSCON_H3_EPHY_ADDR_SHIFT;
> #
>
> -----Original Message-----
> From: [email protected] [mailto:[email protected]] On Behalf Of
> Stephen Graf
> Sent: Sunday, October 22, 2017 9:50 PM
> To: [email protected]; 'Patrick Wildt' <[email protected]>; 'Mark Kettenis'
> <[email protected]>
> Subject: Re: Another step on getting dwxe to work on Allwinner H3
>
> I just noticed Patrick's latest patch that will probably resolve this issue.
> I think I have to reload my sources to the most recent and test again.
>
> -----Original Message-----
> From: [email protected] [mailto:[email protected]] On Behalf Of
> Stephen Graf
> Sent: Saturday, October 21, 2017 10:56 PM
> To: [email protected]; 'Patrick Wildt' <[email protected]>; 'Mark Kettenis'
> <[email protected]>
> Subject: Another step on getting dwxe to work on Allwinner H3
>
> After making changes for the clock divisor shift I was able to see
> transactions with the media device, but the link would not start until I
> discovered that the media isolate bit was being set on the media reset. I
> put the no isolate flag in the ukphy driver and I then thought that I had a
> working driver. I was able to do a dhclient and get a valid ip (see below).
> However within a few seconds the system crashed. On other tests I was able
> to make it crash by doing a ping to the device from another machine or
> trying to connect remotely via ssh.
>
> I am confident that my dtb works and seem to have the driver communicating.
> The system crash is something I don't know how to handle. I know Mark says
> to be patient, but I think I have made significant progress and uncovered a
> few problems that I have been able to work around. I would appreciate some
> guidance on how to tackle the system crash problem.
>
> CHANGES TO ukphy.c (COPIED FROM VARIOUS OTHER PHYS)
> sc->mii_model = MII_MODEL(ma->mii_id2);
> sc->mii_pdata = mii;
> sc->mii_flags = ma->mii_flags;
> sc->mii_flags |= MIIF_NOISOLATE;
>
> CONSOLE BOOT LOG SHOWING DEBUG INFO:
> syscon0 at simplebus0
> sxiccmu1 at simplebus0
> sxipio0 at simplebus0: 94 pins
> sxipio1 at simplebus0: 12 pins
> dwxe0 at simplebus0
> if_dwxe phy-handle node: 0x560.
> if_dwxe sc_phyloc: 0x1.
> if_dwxe sc_clk: 200000000
> if_dwxe sc_clk div_ratio: 0x3
> : address 02:81:b1:07:76:5e
> if_dwxe syscon is not null
> if_dwxe phy_mode: mii
> if_dwxe syscon: 0x168000
> if_dwxe mii read cmd: 0x301011, data: 0x79e9 if_dwxe mii read cmd: 0x301021,
> data: 0x44 if_dwxe mii read cmd: 0x301031, data: 0x1400
> ukphy0 at dwxe0 phy 1: Generic IEEE 802.3u media interface, rev. 0: OUI
> 0x001105, model 0x0000 if_dwxe mii write cmd: 0x301003, data: 0x8000 if_dwxe
> mii read cmd: 0x301001, data: 0x3000 if_dwxe mii read cmd: 0x301011, data:
> 0x79c9 if_dwxe mii read cmd: 0x3010f1, data: 0x0 Adding entry for Ethernet
> 10baseT <master,rxpause,txpause> Adding entry for Ethernet 10baseT
> <full-duplex,master,rxpause,txpause>
> Adding entry for Ethernet 100baseTX <master,rxpause,txpause> Adding entry
> for Ethernet 100baseTX <full-duplex,master,rxpause,txpause>
> Adding entry for Ethernet autoselect <master,rxpause,txpause>
> ifmedia_set: target Ethernet autoselect <master,rxpause,txpause>
> ifmedia_set: setting to Ethernet autoselect <master,rxpause,txpause>
>
> DHCLIENT
> # ifconfig dwxe0
> dwxe0: flags=8802<BROADCAST,SIMPLEX,MULTICAST> mtu 1500
> lladdr 02:81:b1:07:76:5e
> index 1 priority 0 llprio 3
> media: Ethernet autoselect (100baseTX full-duplex)
> status: active
> # dhclient dwxe0
> dwxe0: DHCPREQUEST to 255.255.255.255
> dwxe0: DHCPACK from 192.168.1.253 (cc:5d:4e:ad:f4:0f)
> dwxe0: bound to 192.168.1.61 -- renewal in 43200 seconds #
>
> CONSOL LOG SHOWING CRASH
> if_dwxe mii read cmd: 0x301001, data: 0x3000 if_dwxe mii read cmd: 0x301041,
> data: 0x21e1 if_dwxe mii read cmd: 0x301051, data: 0xc5e1 if_dwxe mii read
> cmd: 0x301011, data: 0x79ed if_dwxe mii read cmd: 0x301011, data: 0x79ed
> if_dwxe mii read cmd: 0x301011, data: 0x79ed if_dwxe mii read cmd: 0x301011,
> data: 0x79ed if_dwxe mii read cmd: 0x301001, data: 0x3000 if_dwxe mii read
> cmd: 0x301041, data: 0x21e1 if_dwxe mii read cmd: 0x301051, data: 0xc5e1
> Fatal kernel mode data abort: 'Alignment fault'
> trapframe: 0xcb1f0e40
> DFSR=00000001, DFAR=c54f481e, spsr=80000013
> r0 =00000221, r1 =00000018, r2 =00000046, r3 =0000002e
> r4 =c5517c00, r5 =c54f480e, r6 =00000001, r7 =00000000
> r8 =cb1f0efc, r9 =cb1f0f00, r10=c0777d84, r11=cb1f0eec r12=cb1f0ef0,
> ssp=cb1f0e90, slr=c05c8d18, pc =c05c87e4
>
> Stopped at ip_input_if+0x118: ldrls r3, [r5, #0x010]
>
>
> -----Original Message-----
> From: [email protected] [mailto:[email protected]] On Behalf Of
> Stephen Graf
> Sent: Friday, October 20, 2017 6:30 PM
> To: [email protected]; 'Patrick Wildt' <[email protected]>
> Cc: 'Mark Kettenis' <[email protected]>
> Subject: dwxe on H3 correction
>
> I took another small step in my quest to get the dwxe driver working on my
> orange pi one (Allwinner H3).
>
> After getting syscon to start before dwxe I think I am able to get through
> the initializations and my dtb seems to have everything that is needed and
> presenting it to the driver.
>
> I now have discovered a little bug that should be fixed. The mio clock
> divisor definitions are made with a left shift of 20 and then when the
> divisors are used in mii read and write they are shifted again. I altered
> the defines to remove the shift:
> #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_SHIFT 20
> //#define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_MASK (0x7 << 20)
> //#define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_16 (0 << 20)
> //#define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_32 (1 << 20)
> //#define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_64 (2 << 20)
> //#define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_128 (3 << 20)
> #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_MASK 0x7
> #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_16 0
> #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_32 1
> #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_64 2
> #define DWXE_MDIO_CMD_MDC_DIV_RATIO_M_128 3
>
>
>
>
