On 09/19/2014 10:55 PM, Slichter, Daniel H. wrote: > This will mean running the I/O single-ended from FPGA onto the > daughterboard and then translating to LVDS, as is done with the > current system.
Why not drive the LVDS signals directly from the FPGA? If doing that I suggest adding some low-capacitance ESD protection/TVS devices (e.g. those designed for HDMI or USB such as RClamp0524P) on the daughterboard, as the FPGA is much more expensive to replace than the buffers. Sébastien _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
