On 01/06/2015 03:26 PM, Sébastien Bourdeauducq wrote: > Or sample SYNC_CLK with a discrete flip-flop or latch near each DDS chip > and trigger them with a skew-matched on-board clocking network pulsed by > the FPGA through a scanned ODELAY. Then low-performance multiplexers, > shared buses and skew are acceptable at the flip-flop outputs.
http://www.onsemi.com/pub/Collateral/NB4L52-D.PDF has 150ps of setup + hold time, so the part-to-part variation in input characteristics should not be significant. And it takes LVCMOS and even contains a comparator. Sébastien _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
