As the topic shifted from backplane logic, I've moved to this conversation to a new thread.
On Tuesday, June 28, 2016 04:02 PM, Grzegorz Kasprowicz wrote: > For synchronisation over fibre we can use existing White Rabbit core. > The card requires only 2 VCXO oscillators and FPGA logic. The WR core > consumes 50% of small Spartan 45T. It ensures 1ns timing accuracy. >We probably won't use White Rabbit as-is, but the basic principle will >be the same. It can be a good idea to include those VCXOs on boards that >may be synchronized over fiber (Kasli/Metlino), though can't we use >instead a Si5324 for jitter cleanup and FPGA PLLs for DDMTD? Heads up that the clock synchronization for Metlino resides on Metlino_clk (Tongue 2) not Metlino_motherboard (Tongue 3-4). So headers need to provide whatever io is required. Greg already has a layout for a Metlino_clk board that has White Rabbit components on it. Greg, do you have a short list of components required for WhiteRabbit-type clock recovery? -Joe _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
