> * The decision we want to taking here is whether we will support only
> the simple hierarchy of a single Metlino *directly* connected to a
> bunch of terminal child devices devices (Sayma, Kasli) or whether we
> allow support for hierarchies deeper than a single level of DRTIO
> links to be built without having to rewrite parts of the stack.

If I wanted a simple hierarchy I'd just use point-to-point BNC cables.
Support of an arbitrary graph (not just hierarchical) is desired.
Routing based on a static lookup table is fine.

> * The slower response times would only affect channels that are deeper
> in the DRTIO tree than the first level. It doesn't degrade performance
> of existing channels. I.e. it affects channels that are on a Sayma
> that's attached to a *satellite* Metlino. And the latency is
> physically given by that hierarchy already. This latency also needs to
> be viewed in comparison to the CPU latency which is µs.

The utility of ARTIQ for future quantum information experiments is
considerably hampered by reliance on CPUs with ~us latency.
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