Hi,
Before DRTIO can operate, the clock chip (HMC* on Sayma and AD9516 on
KC705) needs to be running.
This setup should be done by the comms CPU on the DRTIO master, and the
management CPU on a DRTIO satellite.
For initialization, the comms or management CPU would configure the
clock chips and bring up the JESD links. The clock chip and JESD code
currently in
https://github.com/m-labs/artiq/blob/master/artiq/examples/phaser/startup_kernel.py
should be moved to the Rust runtime and the Rust DRTIO satellite manager.
The SPI core would be connected to the comms CPU.
It seems desirable to alter DAC settings in the experiment. Perhaps this
feature can be deferred. When we need it, it can be done as follows:
* the kernel CPU sends a request to the comms CPU via the mailbox. Since
the comms CPU already knows about the DAC as it needs to initialize it,
the request should be on a similar level of abstraction, i.e. it should
be something like "enable mix mode" and not "write X to SPI register Y".
* if the DAC is on the local board, the comms CPU performs the SPI
transaction.
* if the DAC is on a remote board, the comms CPU sends an auxiliary
DRTIO packet to the relevant board, and its management CPU performs the
SPI transaction, then sends an acknowledgement auxiliary packet back.
Sébastien
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