I concur with Tom and Daniel's observations favoring a larger (100T) FPGA.
On Thu, Jun 29, 2017 at 5:11 PM, Thomas Harty via ARTIQ <[email protected]> wrote: >> Octopart Avnet costs for 1 unit >> >> XC7A100T-2CSG324C $131.22 >> XC7A50T-2CSG324C $74.98 > > FWIW, AFAICT we’d want the FGG484 for the 4 GTPs. Price from Avnet is then > 170EUR for the 100T v 100EUR for the 50T. Cost difference is still something > like 35EUR taking into account Greg’s comment. > > Greg, how much do you think it will cost to buy a complete Kasli? Assuming > it’s something like $500-$1k, the $35 difference in FPGA cost seems like a > non-issue to me. > >> Kasli was meant to be a simple and low-cost board without a backplane, >> and you are now using the backplane as an argument… > > The BP can be a simple break-out adapter, as suggested by Robert. This is our > current plan for running a 16 channel laser servo from a single Kasli. > > T > > > >> On 29 Jun 2017, at 20:55, [email protected] wrote: >> >> Send ARTIQ mailing list submissions to >> [email protected] >> >> To subscribe or unsubscribe via the World Wide Web, visit >> https://ssl.serverraum.org/lists/listinfo/artiq >> or, via email, send a message with subject or body 'help' to >> [email protected] >> >> You can reach the person managing the list at >> [email protected] >> >> When replying, please edit your Subject line so it is more specific >> than "Re: Contents of ARTIQ digest..." >> >> >> Today's Topics: >> >> 1. Re: ARTIQ Digest, Vol 37, Issue 6 (Thomas Harty) >> 2. Re: ARTIQ Digest, Vol 37, Issue 6 (Slichter, Daniel H. (Fed)) >> 3. Re: ARTIQ Digest, Vol 37, Issue 6 (Sébastien Bourdeauducq) >> 4. Re: ARTIQ Digest, Vol 37, Issue 6 (Joe Britton) >> 5. Re: ARTIQ Digest, Vol 37, Issue 6 (Grzegorz Kasprowicz) >> >> >> ---------------------------------------------------------------------- >> >> Message: 1 >> Date: Thu, 29 Jun 2017 10:16:32 +0000 >> From: Thomas Harty <[email protected]> >> To: "[email protected]" <[email protected]> >> Subject: Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6 >> Message-ID: >> <[email protected]> >> Content-Type: text/plain; charset="iso-8859-1" >> >> Sébastien, >> >> Given the relatively low cost of the Artix-7 FPGAs, my preference is >> generally to go as big and as fast as reasonably possible. I don't want to >> find that, for example, we can't fit a hard FPU/fancy servo on Kasli because >> we saved $50 on the FPGA. Also, since gateware development is usually much >> more expensive than hardware, I'd rather go for dumb/inefficient gateware on >> big FPGAs than have to optimise the gateware to fit on a smaller FPGA. >> >> The fact that going for a 75T/100T gives us access to 12EEMs/Kasli (4 on the >> BP) rather than 10EEMs/Kasli (only 2 on the BP) for the 50T is an added >> benefit. >> >> Having said all that, if you think the 50T in the -2 speed grade won't be a >> limitation then I'm happy to go along with your recommendation... >> >> T >> >> ________________________________________ >> From: ARTIQ [[email protected]] on behalf of >> [email protected] [[email protected]] >> Sent: 29 June 2017 11:00 >> To: [email protected] >> Subject: ARTIQ Digest, Vol 37, Issue 6 >> >> Send ARTIQ mailing list submissions to >> [email protected] >> >> To subscribe or unsubscribe via the World Wide Web, visit >> https://ssl.serverraum.org/lists/listinfo/artiq >> or, via email, send a message with subject or body 'help' to >> [email protected] >> >> You can reach the person managing the list at >> [email protected] >> >> When replying, please edit your Subject line so it is more specific >> than "Re: Contents of ARTIQ digest..." >> >> >> Today's Topics: >> >> 1. Kasli FPGA selection (Sébastien Bourdeauducq) >> >> >> ---------------------------------------------------------------------- >> >> Message: 1 >> Date: Thu, 29 Jun 2017 12:23:04 +0800 >> From: Sébastien Bourdeauducq <[email protected]> >> To: Thomas Harty <[email protected]> >> Cc: "[email protected]" <[email protected]>, Grzegorz >> Kasprowicz <[email protected]> >> Subject: [ARTIQ] Kasli FPGA selection >> Message-ID: <[email protected]> >> Content-Type: text/plain; charset=utf-8; format=flowed >> >> On Wednesday, June 28, 2017 04:52 PM, Thomas Harty wrote: >>> Have we settled on the 50T as the FPGA for the first version of Kasli, >>> and what speed grade? >> >> I would advocate for the 50T in -2 speed grade for two main reasons: >> a) I don't think we need that much FPGA resources for the 100T to be needed. >> b) -2 speed grade transceivers go to 6.25Gbps whereas -1 speed grade >> ones go to 3.75Gbps. In addition to a significant increase in bandwidth, >> the -2 transceivers can use the same configuration on the Metlino/Sayma >> side which is used for the backplane (5Gbps). Otherwise we would have to >> generate another set of Ultrascale transceiver settings (and shave a >> yak) and potentially deal with weird RTIO frequency ratios in a hybrid >> MTCA/Eurocard Sinara system. >> >> Sébastien >> >> >> ------------------------------ >> >> Subject: Digest Footer >> >> _______________________________________________ >> ARTIQ mailing list >> https://ssl.serverraum.org/lists/listinfo/artiq >> >> ------------------------------ >> >> End of ARTIQ Digest, Vol 37, Issue 6 >> ************************************ >> >> >> ------------------------------ >> >> Message: 2 >> Date: Thu, 29 Jun 2017 12:27:17 +0000 >> From: "Slichter, Daniel H. (Fed)" <[email protected]> >> To: "'[email protected]'" <[email protected]> >> Subject: Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6 >> Message-ID: >> >> <by1pr09mb05994c1bc69d7602f88fb88191...@by1pr09mb0599.namprd09.prod.outlook.com> >> >> Content-Type: text/plain; charset="iso-8859-1" >> >> I second Tom's thoughts here -- I would go for the largest Artix-7 we can >> reasonably accommodate, just for flexibility. Going with the -2 speed grade >> sounds like it makes a lot of sense. >> >> >> Best, >> >> Daniel >> >> ________________________________ >> From: ARTIQ <[email protected]> on behalf of Thomas Harty via >> ARTIQ <[email protected]> >> Sent: Thursday, June 29, 2017 4:16:32 AM >> To: [email protected] >> Subject: Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6 >> >> Sébastien, >> >> Given the relatively low cost of the Artix-7 FPGAs, my preference is >> generally to go as big and as fast as reasonably possible. I don't want to >> find that, for example, we can't fit a hard FPU/fancy servo on Kasli because >> we saved $50 on the FPGA. Also, since gateware development is usually much >> more expensive than hardware, I'd rather go for dumb/inefficient gateware on >> big FPGAs than have to optimise the gateware to fit on a smaller FPGA. >> >> The fact that going for a 75T/100T gives us access to 12EEMs/Kasli (4 on the >> BP) rather than 10EEMs/Kasli (only 2 on the BP) for the 50T is an added >> benefit. >> >> Having said all that, if you think the 50T in the -2 speed grade won't be a >> limitation then I'm happy to go along with your recommendation... >> >> T >> >> ________________________________________ >> From: ARTIQ [[email protected]] on behalf of >> [email protected] [[email protected]] >> Sent: 29 June 2017 11:00 >> To: [email protected] >> Subject: ARTIQ Digest, Vol 37, Issue 6 >> >> Send ARTIQ mailing list submissions to >> [email protected] >> >> To subscribe or unsubscribe via the World Wide Web, visit >> https://ssl.serverraum.org/lists/listinfo/artiq >> or, via email, send a message with subject or body 'help' to >> [email protected] >> >> You can reach the person managing the list at >> [email protected] >> >> When replying, please edit your Subject line so it is more specific >> than "Re: Contents of ARTIQ digest..." >> >> >> Today's Topics: >> >> 1. Kasli FPGA selection (Sébastien Bourdeauducq) >> >> >> ---------------------------------------------------------------------- >> >> Message: 1 >> Date: Thu, 29 Jun 2017 12:23:04 +0800 >> From: Sébastien Bourdeauducq <[email protected]> >> To: Thomas Harty <[email protected]> >> Cc: "[email protected]" <[email protected]>, Grzegorz >> Kasprowicz <[email protected]> >> Subject: [ARTIQ] Kasli FPGA selection >> Message-ID: <[email protected]> >> Content-Type: text/plain; charset=utf-8; format=flowed >> >> On Wednesday, June 28, 2017 04:52 PM, Thomas Harty wrote: >>> Have we settled on the 50T as the FPGA for the first version of Kasli, >>> and what speed grade? >> >> I would advocate for the 50T in -2 speed grade for two main reasons: >> a) I don't think we need that much FPGA resources for the 100T to be needed. >> b) -2 speed grade transceivers go to 6.25Gbps whereas -1 speed grade >> ones go to 3.75Gbps. In addition to a significant increase in bandwidth, >> the -2 transceivers can use the same configuration on the Metlino/Sayma >> side which is used for the backplane (5Gbps). Otherwise we would have to >> generate another set of Ultrascale transceiver settings (and shave a >> yak) and potentially deal with weird RTIO frequency ratios in a hybrid >> MTCA/Eurocard Sinara system. >> >> Sébastien >> >> >> ------------------------------ >> >> Subject: Digest Footer >> >> _______________________________________________ >> ARTIQ mailing list >> https://ssl.serverraum.org/lists/listinfo/artiq >> >> ------------------------------ >> >> End of ARTIQ Digest, Vol 37, Issue 6 >> ************************************ >> _______________________________________________ >> ARTIQ mailing list >> https://ssl.serverraum.org/lists/listinfo/artiq >> -------------- next part -------------- >> An HTML attachment was scrubbed... >> URL: >> <http://ssl.serverraum.org/lists-archive/artiq/attachments/20170629/dbb942dc/attachment-0001.html> >> >> ------------------------------ >> >> Message: 3 >> Date: Thu, 29 Jun 2017 21:37:27 +0800 >> From: Sébastien Bourdeauducq <[email protected]> >> To: Thomas Harty <[email protected]>, >> "[email protected]" <[email protected]> >> Subject: Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6 >> Message-ID: <[email protected]> >> Content-Type: text/plain; charset=utf-8; format=flowed >> >> On Thursday, June 29, 2017 06:16 PM, Thomas Harty via ARTIQ wrote: >>> The fact that going for a 75T/100T gives us access to 12EEMs/Kasli (4 >>> on the BP) rather than 10EEMs/Kasli (only 2 on the BP) for the 50T is >>> an added benefit. >> Kasli was meant to be a simple and low-cost board without a backplane, >> and you are now using the backplane as an argument... >> >> >> ------------------------------ >> >> Message: 4 >> Date: Thu, 29 Jun 2017 15:43:00 -0400 >> From: Joe Britton <[email protected]> >> To: Sébastien Bourdeauducq <[email protected]> >> Cc: "[email protected]" <[email protected]>, Thomas Harty >> <[email protected]> >> Subject: Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6 >> Message-ID: >> <cae2_b1urfvnzvaiyycvwurgbc5yz9ckw+-xz6+ntbt6+h4f...@mail.gmail.com> >> Content-Type: text/plain; charset="UTF-8" >> >> Octopart Avnet costs for 1 unit >> >> XC7A100T-2CSG324C $131.22 >> XC7A50T-2CSG324C $74.98 >> >> Greg, What is the cost differential between 50T-2 and 100T-2 assuming >> Xilinx open source pricing? -Joe >> >> >> ------------------------------ >> >> Message: 5 >> Date: Thu, 29 Jun 2017 21:55:16 +0200 >> From: Grzegorz Kasprowicz <[email protected]> >> To: Joe Britton <[email protected]> >> Cc: "[email protected]" <[email protected]>, Thomas Harty >> <[email protected]> >> Subject: Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6 >> Message-ID: >> <CAGKrh=ggc-0mweiz123lj5nsnizirbk6dcxeiymnhfejfhi...@mail.gmail.com> >> Content-Type: text/plain; charset="utf-8" >> >> Usually one can expect half of octopart prices. >> So the difference would be about 30$ >> >> On 29 June 2017 at 21:43, Joe Britton via ARTIQ <[email protected]> >> wrote: >> >>> Octopart Avnet costs for 1 unit >>> >>> XC7A100T-2CSG324C $131.22 >>> XC7A50T-2CSG324C $74.98 >>> >>> Greg, What is the cost differential between 50T-2 and 100T-2 assuming >>> Xilinx open source pricing? -Joe >>> _______________________________________________ >>> ARTIQ mailing list >>> https://ssl.serverraum.org/lists/listinfo/artiq >>> >> -------------- next part -------------- >> An HTML attachment was scrubbed... >> URL: >> <http://ssl.serverraum.org/lists-archive/artiq/attachments/20170629/ab4bb70a/attachment.html> >> >> ------------------------------ >> >> Subject: Digest Footer >> >> _______________________________________________ >> ARTIQ mailing list >> https://ssl.serverraum.org/lists/listinfo/artiq >> >> ------------------------------ >> >> End of ARTIQ Digest, Vol 37, Issue 7 >> ************************************ > > _______________________________________________ > ARTIQ mailing list > https://ssl.serverraum.org/lists/listinfo/artiq _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
