Thanks Arpit and Daniel for email responses. Catching up the mailing list...
The path Metlino/Sayma -> FMC -> VHDCI uses LVDS which are driven as
_p and _n pin pairs from the FPGA for each EEM IO line. Each EEM board
has an LVDS receiver that generates local single-ended IO.
> If that is the case, you need to dig into Migen to figure out how to express
> the
> subsignals with two pins using an LVDS standard (I haven’t done this myself,
> you might ask Robert
> or Sebastien).
We've already figure out how to do get Migen to express subsignals
using a pair of pins. For example,
("clk", 0,
Subsignal("p", Pins("Y23")),
Subsignal("n", Pins("Y24")),
IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
)
Does Migen supports sub-subsignals or is a change needed to SPIMaster?
This is what the NIST_clock Migen subsignal definition looks like for
spi when driven single-ended by the FPGA.
("spi", 0,
Subsignal("clk", Pins("LPC:LA13_N")),
Subsignal("cs_n", Pins("LPC:LA14_N")),
Subsignal("mosi", Pins("LPC:LA17_CC_P")),
Subsignal("miso", Pins("LPC:LA17_CC_N")),
IOStandard("LVTTL")),
On Wed, Sep 13, 2017 at 11:21 AM, Joe Britton <[email protected]> wrote:
> What's the right way to use ARTIQ to drive SPI devices across the VHDCI bus?
> The SPIMaster interface appears to take only a single signal for each of
> clk, cs_n, mosi and miso.
>
> Has anybody yet interfaced with an SPI device using VHCDI? -Joe
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