Dale,
>> by assigning a register to the literal pool via LARL at
the beginning of a module, I took a program that had 5 base registers
and now only has one LTORG pointer register.
Which is good, but your sample shows "nothing". All you did is use
LARL to establish the base for the data-area. The rest of your coding
is either converted by hand or by the various available methods to go
without a base. None of them introduced LARL.
When relative+immediate feature became available, LARL was not there.
Hence AHI was used (to get from entry of the program to start of
data-area). There are other techniques as well- see code for a sample.
The problem that John B is addressing is in the following (complete) example:
in front of your code:
CODE LOCTR
DATA LOCTR
BASECOVER DS 0D
CODE LOCTR
JAS R3,*+8
DC AL4(BASECOVER)
L R3,0(,R3)
USING BASECOVER,R3
somewhere (in the code)
LARL R1,=X'23' 1 = see note
and later
LARL R1,=X'45' 2 = see note
somewhere (very later in the code)
DATA LOCTR
LTORG
Note1 = this will assemble without errors (assuming that this is the
first not aligned odd-sized literal)
Note2 = this will fail, if no other odd length literal is in between
--
Martin
Pi_cap_CPU - all you ever need around MWLC/SCRT/CMT in z/VSE
more at http://www.picapcpu.de
