> -----Original Message-----
> From: IBM Mainframe Assembler List
> [mailto:[email protected]] On Behalf Of Paul Gilmartin
> Sent: Tuesday, August 24, 2010 7:44 AM
> To: [email protected]
> Subject: Re: Efficient Memory List
>
<snip>
>
> Are there instructions which perform for cache operations
> analogous to what PGLOAD and PGOUT do for main memory?
> Is anything to be gained by anticipatory fetching from a
> cache line to cause it to be brought from main storage?
> If the result of the fetch is ignored, can it proceed
> concurently, without causing a pipeline stall?
>
> -- gil

On the z196, there is a "cache load" type instruction. I can't find the URL to 
the paper, but I vaguely remember it.

--
John McKown
Systems Engineer IV
IT

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